Searched +full:interrupt +full:- +full:parent (Results 1 – 25 of 906) sorted by relevance
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| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
20 interrupt. Note the rising edge type.
24 - compatible : Should be "altr,socfpga-ocram-ecc"
25 - reg : Address and size for ECC error interrupt clear registers.
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | interrupts.txt | 1 Specifying interrupt information for devices
4 1) Interrupt client nodes
5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
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| D | marvell,icu.txt | 1 Marvell ICU Interrupt Controller
2 --------------------------------
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
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| D | riscv,aplic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
14 platform level interrupt controller (APLIC) for handling wired interrupts
15 in a RISC-V platform. The RISC-V AIA specification can be found at
16 https://github.com/riscv/riscv-aia.
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| D | brcm,bcm6345-l1-intc.txt | 1 Broadcom BCM6345-style Level 1 interrupt controller
3 This block is a first level interrupt controller that is typically connected
8 - 32, 64 or 128 incoming level IRQ lines
10 - Most onchip peripherals are wired directly to an L1 input
12 - A separate instance of the register set for each CPU, allowing individual
15 - Contains one or more enable/status word pairs per CPU
17 - No atomic set/clear operations
19 - No polarity/level/edge settings
21 - No FIFO or priority encoder logic; software is expected to read all
22 2-4 status words to determine which IRQs are pending
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| D | abilis,tb10x-ictl.txt | 1 TB10x Top Level Interrupt Controller
4 The Abilis TB10x SOC contains a custom interrupt controller. It performs
5 one-to-one mapping of external interrupt sources to CPU interrupts and
9 -------------------
11 - compatible: Should be "abilis,tb10x-ictl"
12 - reg: specifies physical base address and size of register range.
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
16 - interrupts: Specifies the list of interrupt lines which are handled by
17 the interrupt controller in the parent controller's notation. Interrupts
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| D | st,spear3xx-shirq.txt | 4 of devices. The multiplexor provides a single interrupt to parent
5 interrupt controller (VIC) on behalf of a group of devices.
14 interrupt multiplexor (one node for all groups). A group in the
15 interrupt controller shares config/control registers with other groups.
16 For example, a 32-bit interrupt enable/disable config register can
17 accommodate up to 4 interrupt groups.
20 - compatible: should be, either of
21 - "st,spear300-shirq"
22 - "st,spear310-shirq"
23 - "st,spear320-shirq"
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| D | amazon,al-fic.txt | 1 Amazon's Annapurna Labs Fabric Interrupt Controller
5 - compatible: should be "amazon,al-fic"
6 - reg: physical base address and size of the registers
7 - interrupt-controller: identifies the node as an interrupt controller
8 - #interrupt-cells : must be 2. Specifies the number of cells needed to encode
9 an interrupt source. Supported trigger types are low-to-high edge
10 triggered and active high level-sensitive.
11 - interrupts: describes which input line in the interrupt parent, this
12 fic's output is connected to. This field property depends on the parent's
16 Interrupt Controllers bindings used by client devices.
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| D | brcm,bcm7038-l1-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7038-style Level 1 interrupt controller
10 This block is a first level interrupt controller that is typically connected
11 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
16 - 64, 96, 128, or 160 incoming level IRQ lines
18 - Most onchip peripherals are wired directly to an L1 input
20 - A separate instance of the register set for each CPU, allowing individual
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| D | brcm,bcm7120-l2-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
10 - Florian Fainelli <f.fainelli@gmail.com>
13 This interrupt controller hardware is a second level interrupt controller that
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
17 Such an interrupt controller has the following hardware design:
19 - outputs multiple interrupts signals towards its interrupt controller parent
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| D | hisilicon,mbigen-v2.txt | 4 Mbigen means: message based interrupt generator.
6 MBI is kind of msi interrupt only used on Non-PCI devices.
8 To reduce the wired interrupt number connected to GIC,
9 Hisilicon designed mbigen to collect and generate interrupt.
12 Non-pci devices can connect to mbigen and generate the
13 interrupt by writing ITS register.
18 -------------------------------------------
19 - compatible: Should be "hisilicon,mbigen-v2"
21 - reg: Specifies the base physical address and size of the Mbigen
25 ------------------------------------------
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| D | fsl,ls-msi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This interrupt controller hardware is a second level interrupt controller that
11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
12 platforms. If interrupt-parent is not provided, the default parent interrupt
15 Each PCIe node needs to have property msi-parent that points to
19 - Frank Li <Frank.Li@nxp.com>
24 - fsl,ls1012a-msi
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| D | nxp,lpc3220-mic.txt | 1 * NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
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| D | open-pic.txt | 4 representation of an Open PIC compliant interrupt controller. This binding is
13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
23 interrupt source. The type shall be a <u32> and the value shall be 2.
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
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| D | technologic,ts4800.txt | 1 TS-4800 FPGA interrupt controller
3 TS-4800 FPGA has an internal interrupt controller. When one of the
5 parent interrupt source.
8 - compatible: should be "technologic,ts4800-irqc"
9 - interrupt-controller: identifies the node as an interrupt controller
10 - reg: physical base address of the controller and length of memory mapped
12 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
14 - interrupts: specifies the interrupt line in the interrupt-parent controller
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| D | realtek,rtl-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek RTL SoC interrupt controller
10 Interrupt controller and router for Realtek MIPS SoCs, allowing each SoC
11 interrupt to be routed to one parent CPU (hardware) interrupt, or left
14 and an interrupt status register is present to indicate which interrupts are
18 - Birger Koblitz <mail@birger-koblitz.de>
19 - Bert Vermeulen <bert@biot.com>
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| D | ti,omap4-wugen-mpu | 1 TI OMAP4 Wake-up Generator
3 All TI OMAP4/5 (and their derivatives) an interrupt controller that
5 is also referred to as "WUGEN-MPU", hence the name of the binding.
9 - compatible : should contain at least "ti,omap4-wugen-mpu" or
10 "ti,omap5-wugen-mpu"
11 - reg : Specifies base physical address and size of the registers.
12 - interrupt-controller : Identifies the node as an interrupt controller.
13 - #interrupt-cells : Specifies the number of cells needed to encode an
14 interrupt source. The value must be 3.
18 - Because this HW ultimately routes interrupts to the GIC, the
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | realtek.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: dsa.yaml#/$defs/ethernet-ports
13 - Linus Walleij <linus.walleij@linaro.org>
20 The SMI "Simple Management Interface" is a two-wire protocol using
21 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
23 SMI-based Realtek devices. The realtek-smi driver is a platform driver
26 The MDIO-connected switches use MDIO protocol to access their registers.
27 The realtek-mdio driver is an MDIO driver and it must be inserted inside
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-xgene-sb.txt | 1 APM X-Gene Standby GPIO controller bindings
3 This is a gpio controller in the standby domain. It also supports interrupt in
4 some particular pins which are sourced to its parent interrupt controller
6 +-----------------+
7 | X-Gene standby |
8 | GPIO controller +------ GPIO_0
9 +------------+ | | ...
10 | Parent IRQ | EXT_INT_0 | +------ GPIO_8/EXT_INT_0
12 | (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
14 | | EXT_INT_N | +------ GPIO_[N+9]
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| D | 8xxx_gpio.txt | 3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
13 interrupt client nodes section) for details how to specify this GPIO
14 module's interrupt.
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
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| /Documentation/devicetree/bindings/serial/ |
| D | lantiq_asc.txt | 4 - compatible : Should be "lantiq,asc"
5 - reg : Address and length of the register set for the device
6 - interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier
7 depends on the interrupt-parent interrupt controller.
10 - clocks: Should contain frequency clock and gate clock
11 - clock-names: Should be "freq" and "asc"
18 interrupt-parent = <&gic>;
23 clock-names = "freq", "asc";
29 interrupt-parent = <&icu0>;
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| /Documentation/devicetree/bindings/net/ |
| D | mdio-mux-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
17 - $ref: /schemas/net/mdio-mux.yaml#
21 const: mdio-mux-gpio
30 - compatible
31 - gpios
36 - |
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
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| /Documentation/devicetree/bindings/pci/ |
| D | ralink,rt3883-pci.txt | 7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
35 - interrupt-controller: identifies the node as an interrupt controller
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| /Documentation/devicetree/bindings/mfd/ |
| D | bfticu.txt | 8 - compatible: "keymile,bfticu"
9 - interrupt-controller: the bfticu FPGA is an interrupt controller
10 - interrupts: the main IRQ line to signal the collected IRQs
11 - #interrupt-cells : is 2 and their usage is compliant to the 2 cells variant
12 of Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
13 - reg: access on the parent local bus (chip select, offset in chip select, size)
17 chassis-mgmt@3,0 {
19 interrupt-controller;
20 #interrupt-cells = <2>;
22 interrupt-parent = <&mpic>;
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