Searched +full:interrupts +full:- +full:extended (Results 1 – 25 of 173) sorted by relevance
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| /Documentation/devicetree/bindings/counter/ |
| D | interrupt-counter.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/counter/interrupt-counter.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Oleksij Rempel <o.rempel@pengutronix.de>
17 Interrupts or gpios are required. If both are defined, the interrupt will
18 take precedence for counting interrupts.
22 const: interrupt-counter
24 interrupts:
31 - compatible
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | thead,c900-aclint-mswi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
10 - Inochi Amaoto <inochiama@outlook.com>
15 - enum:
16 - sophgo,sg2042-aclint-mswi
17 - const: thead,c900-aclint-mswi
22 interrupts-extended:
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| D | riscv,aplic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
14 platform level interrupt controller (APLIC) for handling wired interrupts
15 in a RISC-V platform. The RISC-V AIA specification can be found at
16 https://github.com/riscv/riscv-aia.
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| D | riscv,imsics.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
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| D | interrupts.txt | 5 -------------------------
7 Nodes that describe devices which generate interrupts must contain an
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
13 which the interrupts are routed; see section 2 below for details.
16 interrupt-parent = <&intc1>;
17 interrupts = <5 0>, <6 0>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
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| D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
14 external interrupts in the system to all hart contexts in the system, via
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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| D | arm,gic-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
16 Interrupts (LPI).
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
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| /Documentation/devicetree/bindings/timer/ |
| D | thead,c900-aclint-mtimer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inochi Amaoto <inochiama@outlook.com>
15 - enum:
16 - sophgo,sg2042-aclint-mtimer
17 - const: thead,c900-aclint-mtimer
21 - description: MTIMECMP Registers
23 reg-names:
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| D | riscv,timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
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| D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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| D | mstar,msc313e-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/mstar,msc313e-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Palmer <daniel@0x0f.com>
11 - Romain Perier <romain.perier@gmail.com>
16 - mstar,msc313e-timer
17 - sstar,ssd20xd-timer
22 interrupts:
29 - compatible
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| /Documentation/devicetree/bindings/serial/ |
| D | mvebu-uart.txt | 2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
17 change will then be possible. When provided it should be UART1-clk
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| /Documentation/devicetree/bindings/media/ |
| D | si4713.txt | 4 supporting 76-108 MHz. It includes an RDS encoder and has both, a stereo-analog
5 and a digital interface, which supports I2S, left-justified and a custom
6 DSP-mode format. It is programmable through an I2C interface.
9 - compatible: Should contain "silabs,si4713"
10 - reg: the I2C address of the device
13 - interrupts-extended: Interrupt specifier for the chips interrupt
14 - reset-gpios: GPIO specifier for the chips reset line
15 - vdd-supply: phandle for Vdd regulator
16 - vio-supply: phandle for Vio regulator
25 interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
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| /Documentation/devicetree/bindings/dma/ |
| D | apple,admac.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 The controller has been seen with up to 24 channels. Even-numbered channels
14 are TX-only, odd-numbered are RX-only. Individual channels are coupled to
18 - Martin Povišer <povik+lin@cutebit.org>
21 - $ref: dma-controller.yaml#
26 - enum:
27 - apple,t6000-admac
28 - apple,t8103-admac
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| /Documentation/devicetree/bindings/mfd/ |
| D | kontron,sl28cpld.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Walle <michael@walle.cc>
26 "#address-cells":
29 "#size-cells":
32 "#interrupt-cells":
35 interrupts:
38 interrupt-controller: true
41 "^gpio(@[0-9a-f]+)?$":
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| /Documentation/devicetree/bindings/usb/ |
| D | mediatek,mt6360-tcpc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/mediatek,mt6360-tcpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT6360 Type-C Port Switch and Power Delivery controller
10 - ChiYuan Huang <cy_huang@richtek.com>
13 Mediatek MT6360 is a multi-functional device. It integrates charger, ADC, flash, RGB indicators,
15 This document only describes MT6360 Type-C Port Switch and Power Delivery controller.
20 - mediatek,mt6360-tcpc
22 interrupts:
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| /Documentation/arch/loongarch/ |
| D | irq-chip-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
17 and there are two models of hierarchy (legacy model and extended model).
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | ti,palmas-gpadc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/ti,palmas-gpadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
13 This ADC is often used to provide channels via the io-channels
27 11 DC-DC current probe (how does this work?)
35 const: ti,palmas-gpadc
37 interrupts:
41 "#io-channel-cells":
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,sm6375-pas.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm6375-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - qcom,sm6375-adsp-pas
20 - qcom,sm6375-cdsp-pas
21 - qcom,sm6375-mpss-pas
28 - description: XO clock
30 clock-names:
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| D | qcom,sc8280xp-pas.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc8280xp-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - qcom,sc8280xp-adsp-pas
20 - qcom,sc8280xp-nsp0-pas
21 - qcom,sc8280xp-nsp1-pas
28 - description: XO clock
30 clock-names:
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| /Documentation/devicetree/bindings/power/supply/ |
| D | qcom,pm8941-charger.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/supply/qcom,pm8941-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Switch-Mode Battery Charger and Boost
10 - Sebastian Reichel <sre@kernel.org>
15 - qcom,pm8226-charger
16 - qcom,pm8941-charger
21 interrupts:
23 - description: charge done
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| /Documentation/devicetree/bindings/net/ |
| D | maxlinear,gpy2xx.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Michael Walle <michael@walle.cc>
14 - $ref: ethernet-phy.yaml#
17 maxlinear,use-broken-interrupts:
19 Interrupts are broken on some GPY2xx PHYs in that they keep the
23 interrupts are disabled for this PHY and polling mode is used. If one
31 maxlinear,use-broken-interrupts: [ interrupts ]
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| /Documentation/devicetree/bindings/rtc/ |
| D | mstar,msc313-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/mstar,msc313-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: rtc.yaml#
13 - Daniel Palmer <daniel@0x0f.com>
14 - Romain Perier <romain.perier@gmail.com>
19 - mstar,msc313-rtc
24 interrupts:
27 start-year: true
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| /Documentation/devicetree/bindings/bus/ |
| D | arm,integrator-ap-lm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/arm,integrator-ap-lm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linusw@kernel.org>
17 then have their own specific per-module bindings and they will be described
21 "#address-cells":
24 "#size-cells":
29 - const: arm,integrator-ap-lm
32 dma-ranges: true
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| /Documentation/devicetree/bindings/hwmon/ |
| D | national,lm90.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jean Delvare <jdelvare@suse.com>
11 - Guenter Roeck <linux@roeck-us.net>
16 - adi,adm1032
17 - adi,adt7461
18 - adi,adt7461a
19 - adi,adt7481
20 - dallas,max6646
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