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/Documentation/devicetree/bindings/interrupt-controller/
Dintel,ce4100-ioapic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#
18 from internal sources and from an external I/O APIC (ioapic).
22 Many of the Intel's generic devices like hpet, ioapic, lapic have
32 const: intel,ce4100-ioapic
56 compatible = "intel,ce4100-ioapic";
Dintel,ce4100-lapic.yaml18 from internal sources and from an external I/O APIC (ioapic).
22 Many of the Intel's generic devices like hpet, ioapic, lapic have
/Documentation/translations/zh_CN/core-api/irq/
Dirq-domain.rst185 Device --> IOAPIC -> Interrupt remapping Controller -> Local APIC -> CPU
189 1) IOAPIC 控制器
206 IOAPIC irq_domain (manage IOAPIC delivery entries/pins)
/Documentation/core-api/irq/
Dirq-domain.rst222 Device --> IOAPIC -> Interrupt remapping Controller -> Local APIC -> CPU
226 1) IOAPIC controller
243 IOAPIC irq_domain (manage IOAPIC delivery entries/pins)
/Documentation/virt/
Dne_overview.rst61 APIC and IOAPIC - to get interrupts from virtio-vsock device. The virtio-mmio
/Documentation/virt/kvm/
Dapi.rst844 On x86, creates a virtual ioapic, a virtual PIC (two PICs, nested), and sets up
846 PIC and IOAPIC; GSI 16-23 only go to the IOAPIC.
940 __u32 chip_id; /* 0 = PIC1, 1 = PIC2, 2 = IOAPIC */
945 struct kvm_ioapic_state ioapic;
965 __u32 chip_id; /* 0 = PIC1, 1 = PIC2, 2 = IOAPIC */
970 struct kvm_ioapic_state ioapic;
6899 level-triggered IOAPIC interrupt. This exit only triggers when the
6900 IOAPIC is implemented in userspace (i.e. KVM_CAP_SPLIT_IRQCHIP is enabled);
6901 the userspace IOAPIC should process the EOI and retrigger the interrupt if
7540 IOAPIC and PIC (and also the PIT, even though this has to be enabled
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/Documentation/admin-guide/
Dkernel-parameters.txt33 acpi_apic_instance= [ACPI,IOAPIC,EARLY]
2515 Provide an override to the IOAPIC-ID<->DEVICE-ID
2519 For example, to map IOAPIC-ID decimal 10 to
2525 * To map IOAPIC-ID decimal 10 to PCI device 00:14.0
2528 * To map IOAPIC-ID decimal 10 to PCI segment 0x1 and