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/Documentation/admin-guide/namespaces/
Dcompatibility-list.rst13 - UTS IPC VFS PID User Net
16 IPC X 1
23 1. Both the IPC and the PID namespaces provide IDs to address
29 or IPC shmem/message. The fact is that this ID is only valid
39 The same is true for the IPC namespaces being shared - two users
40 from different user namespaces should not access the same IPC objects
/Documentation/devicetree/bindings/soc/ti/
Dwkup-m3-ipc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Wakeup M3 IPC device
10 - Dave Gerlach <d-gerlach@ti.com>
11 - Drew Fustini <dfustini@baylibre.com>
14 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
17 C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
18 to boot the wkup_m3, it handles communication with the CM3 using IPC registers
[all …]
/Documentation/devicetree/bindings/soc/qcom/
Dqcom,smsm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
25 '#address-cells':
28 qcom,local-host:
42 (0-indexed).
44 '#size-cells':
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Dqcom,rpm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Bjorn Andersson <andersson@kernel.org>
21 - qcom,rpm-apq8064
22 - qcom,rpm-msm8660
23 - qcom,rpm-msm8960
24 - qcom,rpm-ipq8064
25 - qcom,rpm-mdm9615
33 interrupt-names:
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Dqcom,smp2p.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
16 of a single 32-bit value between two processors. Each value has a single
34 qcom,ipc:
35 $ref: /schemas/types.yaml#/definitions/phandle-array
37 - items:
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Dqcom,smd.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18 Using the top-level SMD node is deprecated. Instead, the SMD edges are defined
29 "^smd-edge|rpm$":
30 $ref: /schemas/remoteproc/qcom,smd-edge.yaml#
34 processor of some sort - or in SMD language an "edge". The name of the
[all …]
/Documentation/devicetree/bindings/remoteproc/
Dqcom,smd-edge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,smd-edge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 some sort - or in SMD language an "edge". The name of the edges are not
24 const: smd-edge
29 - qcom,smd-channels
36 - qcom,smd-channels
54 qcom,ipc:
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Dti,k3-m4f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-m4f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hari Nagalla <hnagalla@ti.com>
11 - Mathieu Poirier <mathieu.poirier@linaro.org>
16 the M4F core in isolation without an IPC. Where as some industrial and
18 with IPC communications.
20 $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
25 - ti,am64-m4fss
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Dqcom,rpm-proc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,rpm-proc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konradybcio@kernel.org>
12 - Stephan Gerhold <stephan@gerhold.net>
17 +--------------------------------------------+
18 | RPM subsystem (qcom,rpm-proc) |
20 reset | +---------------+ +-----+ +-----+ |
[all …]
Dti,keystone-rproc.txt5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
15 Each DSP Core sub-system is represented as a single DT node, and should also
22 --------------------
25 - compatible: Should be one of the following,
26 "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
27 "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
28 "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
29 "ti,k2g-dsp" for DSPs on Keystone 2 66AK2G SoCs
31 - reg: Should contain an entry for each value in 'reg-names'.
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/Documentation/devicetree/bindings/mailbox/
Dmtk,adsp-mbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
13 The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC
15 The MTK ADSP mailbox IPC also provides the ability for one processor to
21 - enum:
22 - mediatek,mt8186-adsp-mbox
23 - mediatek,mt8195-adsp-mbox
[all …]
Dbrcm,bcm2835-mbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/brcm,bcm2835-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM2835 VideoCore mailbox IPC
10 - Stefan Wahren <stefan.wahren@i2se.com>
14 const: brcm,bcm2835-mbox
22 "#mbox-cells":
26 - compatible
27 - reg
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Dmailbox.txt9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
15 #mbox-cells = <1>;
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
26 - shmem : List of phandle pointing to the shared memory(SHM) area between the
27 users of these mailboxes for IPC, one for each mailbox. This shared
35 mbox-names = "pwr-ctrl", "rpc";
42 compatible = "mmio-sram";
45 #address-cells = <1>;
46 #size-cells = <1>;
[all …]
Dst,stm32-ipcc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 IPC controller
16 - Fabien Dessenne <fabien.dessenne@foss.st.com>
17 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
21 const: st,stm32mp1-ipcc
31 - description: rx channel occupied
32 - description: tx channel free
[all …]
Dapple,mailbox.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
11 - Sven Peter <sven@svenpeter.dev>
15 messages between the main CPU and a co-processor. Multiple instances
17 One of the two FIFOs is used to send data to a co-processor while the other
19 Various clients implement different IPC protocols based on these simple
25 - description:
30 - enum:
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Dhisilicon,hi6220-mailbox.txt13 --------------------
14 - compatible: Shall be "hisilicon,hi6220-mbox"
15 - reg: Contains the mailbox register address range (base
16 address and length); the first item is for IPC
19 - #mbox-cells: Common mailbox binding property to identify the number
28 - interrupts: Contains the interrupt information for the mailbox
33 --------------------
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
40 --------
43 compatible = "hisilicon,hi6220-mbox";
[all …]
/Documentation/devicetree/bindings/reserved-memory/
Dnvidia,tegra264-bpmp-shmem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra CPU-NS - BPMP IPC reserved memory
10 - Peter De Schrijver <pdeschrijver@nvidia.com>
13 Define a memory region used for communication between CPU-NS and BPMP.
15 has to be known to both CPU-NS and BPMP for correct IPC operation.
16 The memory region is defined using a child node under /reserved-memory.
17 The sub-node is named shmem@<address>.
[all …]
/Documentation/devicetree/bindings/powerpc/nintendo/
Dwii.txt11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
41 - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi"
42 - reg : should contain the PI registers location and length
52 - #interrupt-cells : <1>
[all …]
/Documentation/devicetree/bindings/firmware/
Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 which can create the interprocessor communication (IPC) between the
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
32 - .../clock/clock-bindings.txt
[all …]
Dnvidia,tegra210-bpmp.txt3 The Boot and Power Management Processor (BPMP) is a co-processor found
9 interprocessor communication (IPC) between the CPU and BPMP.
12 - compatible
15 - "nvidia,tegra210-bpmp"
16 - reg: physical base address and length for HW synchornization primitives
19 - interrupts: specifies the interrupt number for receiving messages ("rx")
23 - #clock-cells : Should be 1 for platforms where DRAM clock control is
29 compatible = "nvidia,tegra210-bpmp";
34 interrupt-names = "tx", "rx";
/Documentation/hid/
Dintel-ish-hid.rst6 processing to a dedicated low power co-processor. This allows the core
11 Sensor usage tables. These may be found in tablets, 2-in-1 convertible laptops
27 ----------------- ----------------------
28 | USB HID | --> | ISH HID |
29 ----------------- ----------------------
30 ----------------- ----------------------
31 | USB protocol | --> | ISH Transport |
32 ----------------- ----------------------
33 ----------------- ----------------------
34 | EHCI/XHCI | --> | ISH IPC |
[all …]
/Documentation/virt/gunyah/
Dmessage-queue.rst1 .. SPDX-License-Identifier: GPL-2.0
5 Message queue is a simple low-capacity IPC channel between two virtual machines.
7 message queue is unidirectional and buffered in the hypervisor. A full-duplex
8 IPC channel requires a pair of queues.
32 queue is being used to implement an RPC-like interface.
44 Clear-to-Send.
52 +-------------------+ +-----------------+ +-------------------+
57 | |-------->| | Rx vIRQ | |
58 |gunyah_msgq_send() | Tx vIRQ |Message queue 1 |-------->|gunyah_msgq_recv() |
59 | |<------- | | | |
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dti,keystone-irq.txt7 used by the IPC mechanism used on Keystone SOCs.
10 - compatible: should be "ti,keystone-irq"
11 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
14 - interrupt-controller : Identifies the node as an interrupt controller
15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
17 - interrupts: interrupt reference to primary interrupt controller
24 compatible = "ti,keystone-irq";
25 ti,syscon-dev = <&devctrl 0x2a0>;
27 interrupt-controller;
28 #interrupt-cells = <1>;
[all …]
/Documentation/devicetree/bindings/i2c/
Dnvidia,tegra186-bpmp-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 management I2C bus. Software running on other CPUs must perform IPC to
21 See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
28 const: nvidia,tegra186-bpmp-i2c
30 nvidia,bpmp-bus-id:
[all …]
/Documentation/devicetree/bindings/gpio/
Dgpio-dsp-keystone.txt5 This is one of the component used by the IPC mechanism used on Keystone SOCs.
8 - 8 for C66x CorePacx CPUs 0-7
11 - each GPIO can be configured only as output pin;
12 - setting GPIO value to 1 causes IRQ generation on target DSP core;
13 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
17 - compatible: should be "ti,keystone-dsp-gpio"
18 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
21 - gpio-controller: Marks the device node as a gpio controller.
22 - #gpio-cells: Should be 2.
29 compatible = "ti,keystone-dsp-gpio";
[all …]

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