Searched full:ipc (Results 1 – 25 of 65) sorted by relevance
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| /Documentation/admin-guide/namespaces/ |
| D | compatibility-list.rst | 13 - UTS IPC VFS PID User Net
16 IPC X 1
23 1. Both the IPC and the PID namespaces provide IDs to address
29 or IPC shmem/message. The fact is that this ID is only valid
39 The same is true for the IPC namespaces being shared - two users
40 from different user namespaces should not access the same IPC objects
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | wkup-m3-ipc.yaml | 4 $id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml#
7 title: Wakeup M3 IPC device
18 to boot the wkup_m3, it handles communication with the CM3 using IPC registers
24 A wkup_m3_ipc device node is used to represent the IPC registers within an
52 - ti,am3352-wkup-m3-ipc # for AM33xx SoCs
53 - ti,am4372-wkup-m3-ipc # for AM43xx SoCs
57 The IPC register address space to communicate with the Wakeup M3 processor
67 phandle to the wkup_m3 rproc node so the IPC driver can boot it
71 phandles used by IPC framework to get correct mbox
98 const: ti,am4372-wkup-m3-ipc
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,smsm.yaml | 48 "^qcom,ipc-[1-4]$":
54 - description: u32 representing the ipc bit within the register
56 Three entries specifying the outgoing ipc bit used for signaling the N:th
115 - qcom,ipc-1
117 - qcom,ipc-2
119 - qcom,ipc-3
121 - qcom,ipc-4
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| D | qcom,rpm.yaml | 39 qcom,ipc:
45 - description: u32 representing the ipc bit within the register
47 Three entries specifying the outgoing ipc bit used for signaling the RPM.
60 - qcom,ipc
73 qcom,ipc = <&apcs 0x8 2>;
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| D | qcom,smp2p.yaml | 34 qcom,ipc:
40 - description: u32 representing the ipc bit within the register
42 Three entries specifying the outgoing ipc bit used for signaling the
117 - qcom,ipc
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| D | qcom,smd.yaml | 55 qcom,ipc = <&apcs 8 0>;
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,smd-edge.yaml | 54 qcom,ipc:
60 - description: u32 representing the ipc bit within the register
62 Three entries specifying the outgoing ipc bit used for signaling the
100 - qcom,ipc
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| D | ti,k3-m4f-rproc.yaml | 16 the M4F core in isolation without an IPC. Where as some industrial and
18 with IPC communications.
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| D | qcom,rpm-proc.yaml | 22 IPC interrupts | | ARM Cortex-M3 |--- +-----+ +-----+ |
45 IPC IRQ 0 | | +----------------------+ | | | +--------------------------+ |
50 IPC IRQ 1 | | +----------------------+ | | | +--------------------------+ |
141 qcom,ipc = <&apcs 8 0>;
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| D | ti,keystone-rproc.txt | 63 "vring" - interrupt for virtio based IPC
66 - kick-gpios: Should specify the gpio device needed for the virtio IPC
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| /Documentation/ABI/obsolete/ |
| D | sysfs-driver-intel_pmc_bxt | 1 These files allow sending arbitrary IPC commands to the PMC/SCU which
10 IPC command to the PMC/SCU.
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| /Documentation/devicetree/bindings/mailbox/ |
| D | mtk,adsp-mbox.yaml | 13 The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC
15 The MTK ADSP mailbox IPC also provides the ability for one processor to
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| D | brcm,bcm2835-mbox.yaml | 7 title: Broadcom BCM2835 VideoCore mailbox IPC
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| D | mailbox.txt | 27 users of these mailboxes for IPC, one for each mailbox. This shared
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| D | st,stm32-ipcc.yaml | 7 title: STMicroelectronics STM32 IPC controller
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| D | apple,mailbox.yaml | 19 Various clients implement different IPC protocols based on these simple
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| /Documentation/devicetree/bindings/reserved-memory/ |
| D | nvidia,tegra264-bpmp-shmem.yaml | 7 title: Tegra CPU-NS - BPMP IPC reserved memory
15 has to be known to both CPU-NS and BPMP for correct IPC operation.
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| /Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | wii.txt | 120 1.j) The Inter-Processor Communication (IPC) node
125 - compatible : should be "nintendo,hollywood-ipc"
126 - reg : should contain the IPC registers location and length
127 - interrupts : should contain the IPC interrupt
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| /Documentation/devicetree/bindings/firmware/ |
| D | nvidia,tegra186-bpmp.yaml | 18 which can create the interprocessor communication (IPC) between the
59 The shared memory area for the IPC TX and RX between CPU and BPMP are
83 that the IPC between CPU and BPMP is based on.
88 description: phandle to reserved memory region used for IPC between
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| D | nvidia,tegra210-bpmp.txt | 9 interprocessor communication (IPC) between the CPU and BPMP.
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| /Documentation/hid/ |
| D | intel-ish-hid.rst | 34 | EHCI/XHCI | --> | ISH IPC |
90 | IPC Drivers |
110 Inter Processor Communication (IPC) driver
113 Location: drivers/hid/intel-ish-hid/ipc
115 The IPC message uses memory mapped I/O. The registers are defined in
118 IPC/FW message types
128 RX (e.g. IPC_REG_ISH2HOST_MSG, IPC_REG_HOST2ISH_MSG). The IPC layer maintains
141 Bits 16..19: management command (for IPC management protocol)
148 To abstract HW level IPC communication, a set of callbacks is registered.
193 whether to send over IPC or over DMA; for each transfer the decision is
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| /Documentation/virt/gunyah/ |
| D | message-queue.rst | 5 Message queue is a simple low-capacity IPC channel between two virtual machines.
8 IPC channel requires a pair of queues.
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,keystone-irq.txt | 7 used by the IPC mechanism used on Keystone SOCs.
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| /Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra186-bpmp-i2c.yaml | 16 management I2C bus. Software running on other CPUs must perform IPC to
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-dsp-keystone.txt | 5 This is one of the component used by the IPC mechanism used on Keystone SOCs.
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