Searched full:irq (Results 1 – 25 of 1143) sorted by relevance
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| /Documentation/arch/arm/ |
| D | interrupts.rst | 16 Secondly, the IRQ subsystem.
39 SA1111 IRQ handler, SA1111 IRQs can hold off SMC9196 IRQs indefinitely.
48 We also bring the idea of an IRQ "chip" (mainly to reduce the size of
57 * Acknowledge the IRQ.
58 * If this is a level-based IRQ, then it is expected to mask the IRQ
61 void (*ack)(unsigned int irq);
63 * Mask the IRQ in hardware.
65 void (*mask)(unsigned int irq);
67 * Unmask the IRQ in hardware.
69 void (*unmask)(unsigned int irq);
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| /Documentation/ABI/testing/ |
| D | sysfs-kernel-irq | 1 What: /sys/kernel/irq
9 one subdirectory for each Linux IRQ number.
11 What: /sys/kernel/irq/<irq>/actions
15 Description: The IRQ action chain. A comma-separated list of zero or more
18 What: /sys/kernel/irq/<irq>/chip_name
25 What: /sys/kernel/irq/<irq>/hwirq
30 the underlying hardware IRQ number used for this Linux IRQ.
32 What: /sys/kernel/irq/<irq>/name
36 Description: Human-readable flow handler name as defined by the irq chip
39 What: /sys/kernel/irq/<irq>/per_cpu_count
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| D | sysfs-bus-auxiliary | 6 files, with each file is named as irq number similar to PCI PF
7 or VF's irq number located in msi_irqs directory.
8 These irq files are added and removed dynamically when an IRQ
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | st,stih407-irq-syscfg.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
19 const: st,stih407-irq-syscfg
22 description: Phandle to Cortex-A9 IRQ system config registers
25 st,irq-device:
29 - description: Enable the IRQ of the channel one.
30 - description: Enable the IRQ of the channel two.
36 - description: Enable the IRQ of the channel one.
37 - description: Enable the IRQ of the channel two.
49 - st,irq-device
56 #include <dt-bindings/interrupt-controller/irq-st.h>
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| D | arm,versatile-fpga-irq.txt | 3 One or more FPGA IRQ controllers can be synthesized in an ARM reference board
5 controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
9 - compatible: "arm,versatile-fpga-irq"
12 as the FPGA IRQ controller has no configuration options for interrupt
22 The "oxsemi,ox810se-rps-irq" compatible is deprecated.
27 compatible = "arm,versatile-fpga-irq";
36 - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
37 output is simply connected to the input of another IRQ controller,
38 then the parent IRQ shall be specified in this property.
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| D | cdns,xtensa-pic.txt | 8 When it's 1, the first cell is the internal IRQ number.
9 When it's 2, the first cell is the IRQ number, and the second cell
11 Periferals are usually connected to a fixed external IRQ, but for different
12 core variants it may be mapped to different internal IRQ.
13 IRQ sensitivity and priority are fixed for each core variant and may not be
19 /* one cell: internal irq number,
20 * two cells: second cell == 0: internal irq number
21 * second cell == 1: external irq number
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| D | ti,keystone-irq.txt | 1 Keystone 2 IRQ controller IP
4 host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
5 The IRQ handler running on HOST OS can identify DSP signal source by
10 - compatible: should be "ti,keystone-irq"
24 compatible = "ti,keystone-irq";
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| /Documentation/core-api/irq/ |
| D | irqflags-tracing.rst | 2 IRQ-flags state tracing
7 The "irq-flags tracing" feature "traces" hardirq and softirq state, in
16 are locking APIs that are not used in IRQ context. (the one exception
20 category, because lots of lowlevel assembly code deal with irq-flags
21 state changes. But an architecture can be irq-flags-tracing enabled in a
30 irq-flags-tracing support:
34 closely guards whether the 'real' irq-flags matches the 'virtual'
35 irq-flags state, and complains loudly (and turns itself off) if the
37 irq-flags-tracing is spent in this state: look at the lockdep
40 lockdep complaint in the irq-flags-tracing functions arch support is
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| D | irq-domain.rst | 6 space where each separate IRQ source is assigned a different number.
10 IRQ numbers.
15 mechanisms as the IRQ core system by modelling their interrupt
19 hardware interrupt numbers: whereas in the past, IRQ numbers could
20 be chosen so they matched the hardware IRQ line into the root
25 interrupt numbers, called hardware irq's, from Linux IRQ numbers.
28 irq numbers, but they don't provide any support for reverse mapping of
29 the controller-local IRQ (hwirq) number into the Linux IRQ number
32 The irq_domain library adds mapping between hwirq and IRQ numbers on
39 be easily extended to support other IRQ topology data sources.
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| D | irq-affinity.rst | 2 SMP IRQ affinity
10 /proc/irq/IRQ#/smp_affinity and /proc/irq/IRQ#/smp_affinity_list specify
11 which target CPUs are permitted for a given IRQ source. It's a bitmask
13 allowed to turn off all CPUs, and if an IRQ controller does not support
14 IRQ affinity then the value will not change from the default of all cpus.
16 /proc/irq/default_smp_affinity specifies default affinity mask that applies
17 to all non-active IRQs. Once IRQ is allocated/activated its affinity bitmask
24 [root@moon 44]# cd /proc/irq/44
43 Now lets restrict that IRQ to CPU(4-7).
63 Here is an example of limiting that same irq (44) to cpus 1024 to 1031::
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| D | concepts.rst | 2 What is an IRQ?
5 An IRQ is an interrupt request from a device.
8 sharing an IRQ.
10 An IRQ number is a kernel identifier used to talk about a hardware
15 An IRQ number is an enumeration of the possible interrupt sources on a
21 Architectures can assign additional meaning to the IRQ numbers, and
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| /Documentation/devicetree/bindings/pci/ |
| D | v3-v360epc-pci.txt | 40 interrupts = <17>; /* Bus error IRQ */
56 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
57 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
58 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
59 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
61 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
62 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
63 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
64 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
66 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
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| D | intel,ixp4xx-pci.yaml | 88 <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
89 <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
90 <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
91 <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
92 <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
93 <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
94 <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */
95 <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
96 <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
97 <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */
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| /Documentation/translations/zh_TW/ |
| D | IRQ.txt | 1 Chinese translated version of Documentation/core-api/irq/index.rst
12 Documentation/core-api/irq/index.rst 的繁體中文翻譯
26 何爲 IRQ?
28 一個 IRQ 是來自某個設備的一個中斷請求。目前，它們可以來自一個硬體引腳，
29 或來自一個數據包。多個設備可能連接到同個硬體引腳，從而共享一個 IRQ。
31 一個 IRQ 編號是用於告知硬體中斷源的內核標識。通常情況下，這是一個
35 一個 IRQ 編號是設備上某個可能的中斷源的枚舉。通常情況下，枚舉的編號是
39 架構可以對 IRQ 編號指定額外的含義，在硬體涉及任何手工配置的情況下，
40 是被提倡的。ISA 的 IRQ 是一個分配這類額外含義的典型例子。
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| /Documentation/translations/zh_CN/core-api/irq/ |
| D | irq-affinity.rst | 3 :Original: Documentation/core-api/irq/irq-affinity.rst
12 SMP IRQ 亲和性
20 /proc/irq/IRQ#/smp_affinity和/proc/irq/IRQ#/smp_affinity_list指定了哪些CPU能
23 (IRQ affinity)，那么所有cpu的默认值将保持不变(即关联到所有CPU).
25 /proc/irq/default_smp_affinity指明了适用于所有非激活IRQ的默认亲和性掩码。一旦IRQ被
32 [root@moon 44]# cd /proc/irq/44
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| /Documentation/core-api/ |
| D | genericirq.rst | 4 Linux generic IRQ handling
23 generic IRQ handling layer.
51 This split implementation of high-level IRQ handlers allows us to
56 The original general IRQ implementation used hw_interrupt_type
61 ``ioapic_edge_irq`` IRQ-type which share many of the low-level details but
64 A more natural abstraction is the clean separation of the 'irq flow' and
67 Analysing a couple of architecture's IRQ subsystem implementations
68 reveals that most of them can use a generic set of 'irq flow' methods
71 IRQ flow itself but not in the chip details - and thus provides a more
72 transparent IRQ subsystem design.
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| /Documentation/devicetree/bindings/sound/ |
| D | everest,es8326.yaml | 67 Bit(2) 1 means button press triggers irq, 0 means not.
68 Bit(3) 1 means PIN9 is the irq source for jack detection. When set to 0,
69 bias change on PIN9 do not triggers irq.
70 Bit(4) 1 means PIN27 is the irq source for jack detection.
71 Bit(5) 1 means PIN9 is the irq source after MIC detect.
72 Bit(6) 1 means PIN27 is the irq source after MIC detect.
81 Bit(0-3) 0 means irq pulse equals 512*internal clock
82 1 means irq pulse equals 1024*internal clock
84 7 means irq pulse equals 65536*internal clock
85 8 means irq mutes PA
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| /Documentation/devicetree/bindings/iio/accel/ |
| D | lis302.txt | 36 - st,irq{1,2}-disable: disable IRQ 1/2
37 - st,irq{1,2}-ff-wu-1: raise IRQ 1/2 on FF_WU_1 condition
38 - st,irq{1,2}-ff-wu-2: raise IRQ 1/2 on FF_WU_2 condition
39 - st,irq{1,2}-data-ready: raise IRQ 1/2 on data ready condition
40 - st,irq{1,2}-click: raise IRQ 1/2 on click condition
41 - st,irq-open-drain: consider IRQ lines open-drain
42 - st,irq-active-low: make IRQ lines active low
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| /Documentation/driver-api/gpio/ |
| D | driver.rst | 63 - method to return the IRQ number associated to a given GPIO line
86 atomic context on realtime kernels (inside hard IRQ handlers and similar
260 The IRQ portions of the GPIO block are implemented using an irq_chip, using
261 the header <linux/irq.h>. So this combined driver is utilizing two sub-
262 systems simultaneously: gpio and irq.
264 It is legal for any IRQ consumer to request an IRQ from any irqchip even if it
265 is a combined GPIO+IRQ driver. The basic premise is that gpio_chip and
269 gpiod_to_irq() is just a convenience function to figure out the IRQ for a
271 the IRQ is used.
293 irq line to a parent interrupt controller one level up. There is no need
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| /Documentation/trace/ |
| D | timerlat-tracer.rst | 36 <idle>-0 [000] d.h1 54.029328: #1 context irq timer_latency 932 ns
38 <idle>-0 [001] dNh1 54.029346: #1 context irq timer_latency 2833 ns
40 <idle>-0 [000] d.h1 54.030328: #2 context irq timer_latency 769 ns
42 <idle>-0 [001] d.h1 54.030344: #2 context irq timer_latency 935 ns
50 ID field serves to relate the *irq* execution to its respective *thread*
53 The *irq*/*thread* splitting is important to clarify in which context
54 the unexpected high value is coming from. The *irq* context can be
72 timer latency at the *irq* context higher than the configured
77 - print_stack: save the stack of the IRQ occurrence. The stack is printed
78 after the *thread context* event, or at the IRQ handler if *stop_tracing_us*
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| /Documentation/driver-api/hte/ |
| D | tegra-hte.rst | 10 (Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the timestamp
34 LIC (Legacy Interrupt Controller) IRQ GTE
37 This GTE instance timestamps LIC IRQ lines in real time. The hte devicetree
39 provides an example of how a consumer can request an IRQ line. Since it is a
40 one-to-one mapping with IRQ GTE provider, consumers can simply specify the IRQ
44 The provider source code of both IRQ and GPIO GTE instances is located at
46 ``drivers/hte/hte-tegra194-test.c`` demonstrates HTE API usage for both IRQ
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| /Documentation/misc-devices/ |
| D | pci-endpoint-test.rst | 16 #) raise legacy IRQ
17 #) raise MSI IRQ
18 #) raise MSI-X IRQ
34 Tests legacy IRQ
42 Changes driver IRQ type configuration. The IRQ type
45 Gets driver IRQ type configuration.
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| /Documentation/scsi/ |
| D | g_NCR5380.rst | 21 If the irq parameter is 254 or is omitted entirely, the driver will probe
22 for the correct IRQ line automatically. If the irq parameter is 0 or 255
23 then no IRQ will be used.
37 irq=xx[,...] the interrupt(s)
65 modprobe g_NCR5380 irq=5 base=0x350 card=1
71 E.g. a port mapped NCR5380 board, driver to probe for IRQ::
79 E.g. a memory mapped NCR53C400 board with no IRQ::
81 modprobe g_NCR5380 irq=255 base=0xc8000 card=1
87 E.g. two cards, DTC3181 (in non-PnP mode) at 0x240 with no IRQ
88 and HP C2502 at 0x300 with IRQ 7::
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| /Documentation/devicetree/bindings/rtc/ |
| D | isil,isl12057.txt | 10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
26 the availability of an IRQ line connected to the SoC.
29 Example isl12057 node without IRQ#2 pin connected (no alarm support):
37 Example isl12057 node with IRQ#2 pin connected to main SoC via MPP6 (note
40 SoC, and the main function of the MPP used as IRQ line, i.e.
67 Example isl12057 node without IRQ#2 pin connected to the SoC but to a
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| /Documentation/power/ |
| D | suspend-and-interrupts.rst | 43 The IRQF_NO_SUSPEND flag is used to indicate that to the IRQ subsystem when
45 leave the corresponding IRQ enabled so as to allow the interrupt to work as
50 Note that the IRQF_NO_SUSPEND flag affects the entire IRQ and not just one
51 user of it. Thus, if the IRQ is shared, all of the interrupt handlers installed
54 the IRQ's users. For this reason, using IRQF_NO_SUSPEND and IRQF_SHARED at the
75 The IRQ subsystem provides two helper functions to be used by device drivers for
77 handling the given IRQ as a system wakeup interrupt line and disable_irq_wake()
80 Calling enable_irq_wake() causes suspend_device_irqs() to treat the given IRQ
81 in a special way. Namely, the IRQ remains enabled, but on the first interrupt
105 IRQ subsystem to trigger a system wakeup.
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