Searched +full:is +full:- +full:decoded +full:- +full:cs (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Michal Simek <michal.simek@amd.com>13 - $ref: spi-controller.yaml#18 - cdns,spi-r1p619 - xlnx,zynq-spi-r1p627 clock-names:29 - const: ref_clk[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Vaishnav Achath <vaishnav.a@ti.com>13 - $ref: spi-controller.yaml#14 - if:18 const: xlnx,versal-ospi-1.021 - power-domains22 - if:[all …]
10 - compatible : Should contain one of the following:11 For Tegra20 must contain "nvidia,tegra20-gmi".12 For Tegra30 must contain "nvidia,tegra30-gmi".13 - reg: Should contain GMI controller registers location and length.14 - clocks: Must contain an entry for each entry in clock-names.15 - clock-names: Must include the following entries: "gmi"16 - resets : Must contain an entry for each entry in reset-names.17 - reset-names : Must include the following entries: "gmi"18 - #address-cells: The number of cells used to represent physical base20 - #size-cells: The number of cells used to represent the size of an address[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#11 external memory (such as NAND or other memory-mapped peripherals) whereas20 Apparently this bus is clocked at 64MHz. It has dedicated pins on the package25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.28 memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)[all …]