Searched +full:ixp42x +full:- +full:expansion +full:- +full:bus +full:- +full:controller (Results 1 – 3 of 3) sorted by relevance
| /Documentation/devicetree/bindings/memory-controllers/ |
| D | intel,ixp4xx-expansion-bus-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel IXP4xx Expansion Bus Controller
10 The IXP4xx expansion bus controller handles access to devices on the
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
12 including IXP42x, IXP43x, IXP45x and IXP46x.
15 - Linus Walleij <linus.walleij@linaro.org>
19 pattern: '^bus@[0-9a-f]+$'
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| D | intel,ixp4xx-expansion-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral properties for Intel IXP4xx Expansion Bus
10 The IXP4xx expansion bus controller handles access to devices on the
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
12 including IXP42x, IXP43x, IXP45x and IXP46x.
15 - Linus Walleij <linus.walleij@linaro.org>
18 intel,ixp4xx-eb-t1:
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| /Documentation/arch/arm/ |
| D | ixp4xx.rst | 6 -------------------------------------------------------------------------
17 integration such as an on-chip I2C controller.
30 - Dual serial ports
31 - PCI interface
32 - Flash access (MTD/JFFS)
33 - I2C through GPIO on IXP42x
34 - GPIO for input/output/interrupts
35 See arch/arm/mach-ixp4xx/include/mach/platform.h for access functions.
36 - Timers (watchdog, OS)
41 - USB device interface
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