Searched full:khz (Results 1 – 25 of 176) sorted by relevance
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| /Documentation/fb/ |
| D | viafb.modes | 14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
81 # Scan Frequency 50.900 kHz 100.00 Hz
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
102 # Scan Frequency 61.800 kHz 120.00 Hz
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| /Documentation/devicetree/bindings/clock/ |
| D | lpc1850-creg-clk.txt | 5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
9 The 32 kHz can also be routed to other peripherals to enable low
21 Shall contain a phandle to the fixed 32 kHz crystal.
28 0 1 kHz clock
29 1 32 kHz Oscillator
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| D | clk-palmas-clk32kg-clocks.txt | 1 * Palmas 32KHz clocks *
3 Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
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| D | samsung,s2mps11.yaml | 16 The S2MPS11/13/15 and S5M8767 provide three(AP/CP/BT) buffered 32.768 kHz
17 outputs. The S2MPS14 provides two (AP/BT) buffered 32.768 KHz outputs.
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| D | maxim,max77686.txt | 10 The MAX77686 contains three 32.768khz clock outputs that can be controlled
15 The MAX77802 contains two 32.768khz clock outputs that can be controlled
19 The MAX77686 contains one 32.768khz clock outputs that can be controlled
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| /Documentation/devicetree/bindings/sound/ |
| D | ti,j721e-cpb-audio.yaml | 18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
89 - description: Parent for CPB_SCKI clock (for 44.1KHz)
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| D | ti,j721e-cpb-ivi-audio.yaml | 23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
82 - description: Parent for IVI_McASP auxclk (for 48KHz)
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| D | ti,pcm6240.yaml | 38 ti,adc3120: Stereo-channel, 768-kHz, Burr-Brown™ audio analog-to-
41 ti,adc5120: 2-Channel, 768-kHz, Burr-Brown™ Audio ADC with 120-dB SNR.
43 ti,adc6120: Stereo-channel, 768-kHz, Burr-Brown™ audio analog-to-
46 ti,dix4192: 216-kHz digital audio converter with Quad-Channel In
52 ti,pcm3120: Automotive, stereo, 106-dB SNR, 768-kHz, low-power
55 ti,pcm3140: Automotive, Quad-Channel, 768-kHz, Burr-Brown™ Audio ADC
58 ti,pcm5120: Automotive, stereo, 120-dB SNR, 768-kHz, low-power
61 ti,pcm5140: Automotive, Quad-Channel, 768-kHz, Burr-Brown™ Audio ADC
64 ti,pcm6120: Automotive, stereo, 123-dB SNR, 768-kHz, low-power
67 ti,pcm6140: Automotive, Quad-Channel, 768-kHz, Burr-Brown™ Audio ADC
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| D | option,gtm601.yaml | 19 - description: Broadmobi BM818 (48Khz stereo)
23 - description: GTM601 (8kHz mono)
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| D | st,stm32-sai.yaml | 152 - description: x8k, SAI parent clock for sampling rates multiple of 8kHz.
153 - description: x11k, SAI parent clock for sampling rates multiple of 11.025kHz.
164 - description: x8k, SAI parent clock for sampling rates multiple of 8kHz.
165 - description: x11k, SAI parent clock for sampling rates multiple of 11.025kHz.
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| /Documentation/i2c/busses/ |
| D | i2c-ismt.rst | 21 Specify the bus speed in kHz.
27 80 kHz
28 100 kHz
29 400 kHz
30 1000 kHz
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| /Documentation/arch/arm/sunxi/ |
| D | clocks.rst | 18 24MHz 32kHz
26 When you are about to suspend, you switch the CPU Mux to the 32kHz
29 24Mhz 32kHz
39 32kHz
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| /Documentation/sound/cards/ |
| D | audiophile-usb.rst | 48 * sample rate from 8kHz to 96kHz
57 * 16-bit/48kHz ==> 4 channels in + 4 channels out
61 * 24-bit/48kHz ==> 4 channels in + 2 channels out,
66 * 24-bit/96kHz ==> 2 channels in _or_ 2 channels out (half duplex only)
197 - 16bits 48kHz mode with Di disabled
204 - 16bits 48kHz mode with Di enabled
234 - 24bits 48kHz mode with Di disabled
241 - 24bits 48kHz mode with Di enabled
249 - 24bits 96kHz mode
266 - 16bits 48kHz mode with only the Do port enabled
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| /Documentation/userspace-api/media/dvb/ |
| D | fe-set-tone.rst | 13 FE_SET_TONE - Sets/resets the generation of the continuous 22kHz tone.
34 This ioctl is used to set the generation of the continuous 22kHz tone.
38 to send a 22kHz tone in order to select between high/low band on some
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| D | fe-diseqc-send-burst.rst | 13 FE_DISEQC_SEND_BURST - Sends a 22KHz tone burst for 2x1 mini DiSEqC satellite selection.
34 This ioctl is used to set the generation of a 22kHz tone burst for mini
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| /Documentation/ABI/testing/ |
| D | sysfs-class-rtc-rtc0-device-rtc_calibration | 7 calibrate the AB8500.s 32KHz Real Time Clock.
12 30.5 micro-seconds (half-parts-per-million of the 32KHz clock)
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| /Documentation/devicetree/bindings/pwm/ |
| D | kontron,sl28cpld-pwm.yaml | 17 frequencies (250Hz, 500Hz, 1kHz, 2kHz).
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| /Documentation/hwmon/ |
| D | mcp3021.rst | 36 compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are
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| D | lm85.rst | 153 driven by a 22.5 kHz clock. This is a global mode, not per-PWM output,
154 which means that setting any PWM frequency above 11.3 kHz will switch
155 all 3 PWM outputs to a 22.5 kHz frequency. Conversely, setting any PWM
156 frequency below 11.3 kHz will switch all 3 PWM outputs to a frequency
179 The LM96000 supports additional high frequency PWM modes (22.5 kHz, 24 kHz,
180 25.7 kHz, 27.7 kHz and 30 kHz), which can be configured on a per-PWM basis.
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| D | g760a.rst | 24 cycle counts of an assumed 32kHz clock source.
30 from the measured speed pulse period by assuming again a 32kHz clock
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| /Documentation/devicetree/bindings/regulator/ |
| D | richtek,rt6245-regulator.yaml | 63 Buck switch frequency selection. Each respective value means 400KHz,
64 800KHz, 1200KHz. If this property is missing then keep in chip default.
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| /Documentation/devicetree/bindings/iio/frequency/ |
| D | adi,admv4420.yaml | 28 adi,lo-freq-khz:
55 adi,lo-freq-khz = <16750000>;
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| /Documentation/devicetree/bindings/opp/ |
| D | opp-v1.yaml | 28 - description: Frequency in kHz
45 /* kHz uV */
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| /Documentation/devicetree/bindings/mfd/ |
| D | max77620.txt | 36 with internal regulators. 32KHz clock can be programmed to be part of a
46 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
54 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
58 and 32KHz clock get disabled at
68 regulators, GPIOs and 32kHz clocks are provided in their respective
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| D | mxs-lradc.txt | 18 2 kHz and its default is 2 (= 1 ms)
20 1 ... 2047. It counts at 2 kHz and its default is
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