| /Documentation/devicetree/bindings/cache/ |
| D | freescale-l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
16 "fsl,mpc8541-l2-cache-controller"
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| D | baikal,bt1-l2-ctl.yaml | 5 $id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
8 title: Baikal-T1 L2-cache Control Block
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
17 L2-cache controller block is responsible for the tuning. Its DT node is
22 const: baikal,bt1-l2-ctl
27 baikal,l2-ws-latency:
34 baikal,l2-tag-latency:
41 baikal,l2-data-latency:
55 l2@1f04d028 {
56 compatible = "baikal,bt1-l2-ctl";
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| D | l2c2x0.yaml | 7 title: ARM L2 Cache Controller
15 implementations of the L2 cache controller have compatible programming
21 Note 1: The description in this document doesn't apply to integrated L2
23 integrated L2 controllers are assumed to be all preconfigured by
40 # offset needs to be added to the address before passing down to the L2
45 # maintenance operations on L1 are broadcasted to the L2 and L2
124 description: If present then L2 is forced to Write through mode
166 description: enable parity checking on the L2 cache (L220 or PL310).
170 description: disable parity checking on the L2 cache (L220 or PL310).
174 description: enable ECC protection on the L2 cache
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| D | marvell,feroceon-cache.txt | 8 - reg : Address of the L2 cache control register. Mandatory for
13 l2: l2-cache@20128 {
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| D | marvell,tauros2-cache.txt | 14 L2: l2-cache {
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| D | socionext,uniphier-system-cache.yaml | 66 // System with L2.
78 // System with L2 and L3.
79 // L2 should specify the next level cache by 'next-level-cache'.
80 l2: cache-controller@500c0000 {
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,l2-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,l2-intc.yaml#
20 - brcm,hif-spi-l2-intc
21 - brcm,upg-aux-aon-l2-intc
22 - const: brcm,l2-intc
25 - brcm,bcm2711-l2-intc
26 - const: brcm,l2-intc
28 - const: brcm,bcm7271-l2-intc
30 - const: brcm,l2-intc
51 If present, this means the L2 controller can be used as a wakeup source
66 compatible = "brcm,l2-intc";
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| D | brcm,bcm7120-l2-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
79 - brcm,bcm7120-l2-intc
80 - brcm,bcm3380-l2-intc
108 If present, this means the L2 controller can be used as a wakeup source
133 compatible = "brcm,bcm7120-l2-intc";
145 compatible = "brcm,bcm3380-l2-intc";
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | brcm,stb-avs-cpu-freq.txt | 6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
13 has been processed. See [2] for more information on the brcm,l2-intc node.
19 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
37 Node brcm,avs-cpu-l2-intr
41 - compatible: must include: brcm,avs-cpu-l2-intr and
42 should include: one of brcm,bcm7271-avs-cpu-l2-intr or
43 brcm,bcm7268-avs-cpu-l2-intr
55 compatible = "brcm,l2-intc";
72 avs-cpu-l2-intr@f04d1100 {
73 compatible = "brcm,bcm7271-avs-cpu-l2-intr",
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| D | cpufreq-dt.txt | 33 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
59 next-level-cache = <&L2>;
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| D | cpufreq-qcom-hw.yaml | 229 L2_0: l2-cache {
250 L2_100: l2-cache {
266 L2_200: l2-cache {
282 L2_300: l2-cache {
298 L2_400: l2-cache {
314 L2_500: l2-cache {
330 L2_600: l2-cache {
346 L2_700: l2-cache {
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,saw2.yaml | 29 - qcom,ipq4019-saw2-l2
31 - qcom,sdm660-gold-saw2-v4.1-l2
32 - qcom,sdm660-silver-saw2-v4.1-l2
33 - qcom,msm8998-gold-saw2-v4.1-l2
34 - qcom,msm8998-silver-saw2-v4.1-l2
39 - qcom,msm8226-saw2-v2.1-l2
42 - qcom,msm8974-saw2-v2.1-l2
43 - qcom,msm8976-gold-saw2-v2.3-l2
44 - qcom,msm8976-silver-saw2-v2.3-l2
46 - qcom,apq8084-saw2-v2.1-l2
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| /Documentation/devicetree/bindings/arm/calxeda/ |
| D | l2ecc.yaml | 7 title: Calxeda Highbank L2 cache ECC
10 Binding for the Calxeda Highbank L2 cache controller ECC device.
11 This does not cover the actual L2 cache controller control registers,
19 const: calxeda,hb-sregs-l2-ecc
39 compatible = "calxeda,hb-sregs-l2-ecc";
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| /Documentation/devicetree/bindings/regulator/ |
| D | qcom,smd-rpm-regulator.yaml | 25 For mp5496, s1, s2, l2, l5
27 For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
30 For pm6125 s1, s2, s3, s4, s5, s6, s7, s8, l1, l2, l3, l5, l6, l7, l8, l9,
33 For pm660, s1, s2, s3, s4, s5, s6, l1, l2, l3, l5, l6, l7, l8, l9, l10, l22,
36 For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob
38 For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10,
44 For pm8909, s1, s2, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
47 For pm8916, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
50 For pm8937, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10,
53 For pm8941, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
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| D | qcom,rpmh-regulator.yaml | 144 vdd-l2-l3-supply: true
165 vdd-l2-l3-supply: true
180 vdd-l2-l3-supply: true
197 vdd-l2-supply: true
212 vdd-l2-l7-supply: true
250 vdd-l1-l2-supply: true
265 vdd-l2-l10-supply: true
281 vdd-l2-l3-supply: true
297 vdd-l2-l7-supply: true
314 vdd-l2-l8-supply: true
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| D | qcom,rpm-regulator.yaml | 19 For pm8058 l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15,
23 For pm8901 l0, l1, l2, l3, l4, l5, l6, s0, s1, s2, s3, s4, lvs0, lvs1, lvs2, lvs3,
26 For pm8921 s1, s2, s3, s4, s7, s8, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
31 For pm8018 s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
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| /Documentation/networking/ |
| D | ipvlan.rst | 14 the master device share the L2 with its slave devices. I have developed this
36 MODE: l3 (default) | l3s | l2
45 (b) This command will create IPvlan link in L2 bridge mode::
47 bash# ip link add link eth0 name ipvl0 type ipvlan mode l2 bridge
49 (c) This command will create an IPvlan device in L2 private mode::
51 bash# ip link add link eth0 name ipvlan type ipvlan mode l2 private
53 (d) This command will create an IPvlan device in L2 vepa mode::
55 bash# ip link add link eth0 name ipvlan type ipvlan mode l2 vepa
61 IPvlan has two modes of operation - L2 and L3. For a given master device,
68 4.1 L2 mode:
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| /Documentation/virt/kvm/x86/ |
| D | running-nested-guests.rst | 14 | L2 | | L2 |
36 - L2 – level-2 guest; a VM running on L1, this is the "nested guest"
45 metal, running the LPAR hypervisor), L1 (host hypervisor), L2
49 L1, and L2) for all architectures; and will largely focus on
139 .. note:: If you suspect your L2 (i.e. nested guest) is running slower,
191 On AMD systems, once an L1 guest has started an L2 guest, the L1 guest
193 "savevm"/"loadvm") until the L2 guest shuts down. Attempting to migrate
194 or save-and-load an L1 guest while an L2 guest is running will result in
199 actually running L2 guests, is expected to function normally even on AMD
202 Migrating an L2 guest is always expected to succeed, so all the following
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| /Documentation/arch/powerpc/ |
| D | kvm-nested.rst | 12 hypervisor has implemented them. The terms L0, L1, and L2 are used to
16 and controlled by L0. L2 is a guest virtual machine that is initiated
39 call made by the L1 to tell the L0 to start an L2 vCPU with the given
40 state. The L0 then starts this L2 and runs until an L2 exit condition
41 is reached. Once the L2 exits, the state of the L2 is given back to
42 the L1 by the L0. The full L2 vCPU state is always transferred from
43 and to L1 when the L2 is run. The L0 doesn't keep any state on the L2
44 vCPU (except in the short sequence in the L0 on L1 -> L2 entry and L2
52 The L1 may run any L2 or vCPU without first informing the L0. It
61 The new PAPR API changes from the v1 API such that the creating L2 and
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| /Documentation/locking/ |
| D | lockdep-design.rst | 22 dependency can be understood as lock order, where L1 -> L2 suggests that
23 a task is attempting to acquire L2 while holding L1. From lockdep's
24 perspective, the two locks (L1 and L2) are not necessarily related; that
145 <L1> -> <L2>
146 <L2> -> <L1>
521 L1 -> L2
523 , which means lockdep has seen L1 held before L2 held in the same context at runtime.
524 And in deadlock detection, we care whether we could get blocked on L2 with L1 held,
525 IOW, whether there is a locker L3 that L1 blocks L3 and L2 gets blocked by L3. So
526 we only care about 1) what L1 blocks and 2) what blocks L2. As a result, we can combine
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| D | rt-mutex-design.rst | 139 Mutexes: L1, L2, L3, L4
143 B owns L2
144 C blocked on L2
152 E->L4->D->L3->C->L2->B->L1->A
166 E->L4->D->L3->C->L2-+
178 blocked on mutex L2::
180 G->L2->B->L1->A
186 +->L2-+
230 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
231 The following shows a locking order of L1->L2->L3, but may not actually
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| /Documentation/translations/it_IT/locking/ |
| D | lockdep-design.rst | 21 possono essere interpretate come il loro ordine; per esempio L1 -> L2 suggerisce
22 che un processo cerca di acquisire L2 mentre già trattiene L1. Dal punto di
23 vista di lockdep, i due blocchi (L1 ed L2) non sono per forza correlati: quella
143 <L1> -> <L2>
144 <L2> -> <L1>
531 L1 -> L2
533 Questo significa che lockdep ha visto acquisire L1 prima di L2 nello stesso
535 interessa sapere se possiamo rimanere bloccati da L2 mentre L1 viene trattenuto.
537 da L1 e un L2 che viene bloccato da L3. Dunque, siamo interessati a (1) quello
538 che L1 blocca e (2) quello che blocca L2. Di conseguenza, possiamo combinare
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| /Documentation/admin-guide/perf/ |
| D | qcom_l2_pmu.rst | 5 This driver supports the L2 cache clusters found in Qualcomm Technologies
6 Centriq SoCs. There are multiple physical L2 cache clusters, each with their
9 There is one logical L2 PMU exposed, which aggregates the results from
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| /Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 10 2 = nbclk (L2 Cache clock)
17 2 = l2clk (L2 Cache clock)
23 2 = l2clk (L2 Cache clock)
43 2 = l2clk (L2 Cache clock derived from CPU0 clock)
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| /Documentation/driver-api/ |
| D | edac.rst | 155 - CPU caches (L1 and L2)
165 For example, a cache could be composed of L1, L2 and L3 levels of cache.
166 Each CPU core would have its own L1 cache, while sharing L2 and maybe L3
174 cpu/cpu0/.. <L1 and L2 block directory>
177 /L2-cache/ce_count
179 cpu/cpu1/.. <L1 and L2 block directory>
182 /L2-cache/ce_count
186 the L1 and L2 directories would be "edac_device_block's"
|