Searched full:latch (Results 1 – 25 of 30) sorted by relevance
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| /Documentation/driver-api/surface_aggregator/clients/ |
| D | dtx.rst | 39 * **Latch:**
55 Latch States
58 The latch mechanism has two major states: *open* and *closed*. In the
62 The latch can additionally be locked and, correspondingly, unlocked, which
66 documentation for the detachment procedure below. By default, the latch is
82 instructions/commands. In case the latch is unlocked, the led will flash
83 green. If the latch has been locked, the led will be solid red
93 - If the latch is unlocked, the EC will open the latch and the clipboard
98 - If the latch is locked, the EC will *not* open the latch, meaning the
111 latch, after which the user can separate clipboard and base.
[all …]
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| /Documentation/devicetree/bindings/gpio/ |
| D | sprd,gpio-eic.yaml | 19 controller contains 4 sub-modules, i.e. EIC-debounce, EIC-latch, EIC-async and
32 The EIC-latch sub-module is used to latch some special power down signals
33 and generate interrupts, since the EIC-latch does not depend on the APB
48 - sprd,sc9860-eic-latch
58 - sprd,ums512-eic-latch
59 - const: sprd,sc9860-eic-latch
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| D | gpio-latch.yaml | 4 $id: http://devicetree.org/schemas/gpio/gpio-latch.yaml#
7 title: GPIO latch controller
43 of number of latches and the number of inputs per latch is derived from
48 const: gpio-latch
53 description: Array of GPIOs to be used to clock a latch
56 description: Array of GPIOs to be used as inputs per latch
59 description: Delay in nanoseconds to wait after the latch inputs have been
80 gpio-latch {
84 compatible = "gpio-latch";
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| /Documentation/devicetree/bindings/clock/ |
| D | armada3700-xtal-clock.txt | 4 reading the gpio latch register.
7 of the GPIO block where the gpio latch is located.
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| /Documentation/devicetree/bindings/mtd/ |
| D | fsl-upm-nand.txt | 6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
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| D | atmel-nand.txt | 125 - atmel,nand-addr-offset : offset for the address latch.
126 - atmel,nand-cmd-offset : offset for the command latch.
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | mux.txt | 50 - ti,latch-bit : latch the mux value to HW, only needed if the register
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| D | divider.txt | 76 - ti,latch-bit : latch the divider value to HW, only needed if the register
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| /Documentation/w1/slaves/ |
| D | w1_ds2413.rst | 30 Bit 1: PIOA Output Latch State
32 Bit 3: PIOB Output Latch State
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | maxim,max34408.yaml | 53 SHTDN Enable Input. CMOS digital input. Connect to GND to clear the latch and
55 delay. Connect to VDD to enable normal latch operation of the SHTDN output.
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| /Documentation/devicetree/bindings/spi/ |
| D | mediatek,spi-mtk-snfi.yaml | 48 mediatek,rx-latch-latency-ns:
49 description: Data read latch latency, unit is nanoseconds.
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| D | cdns,qspi-nor.yaml | 127 Flag to indicate that QSPI return clock is used to latch the read
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| /Documentation/hwmon/ |
| D | adm9240.rst | 178 a 20 ms active low pulse to reset an external Chassis Intrusion latch.
180 Clear the CI latch by writing value 0 to the sysfs intrusion0_alarm file.
200 that alarm bits may be cleared on read, user-space may latch alarms and
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| /Documentation/devicetree/bindings/mmc/ |
| D | mtk-sd.yaml | 129 Gear of the third delay line for DS for input data latch in data
138 mediatek,latch-ck:
141 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
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| /Documentation/virt/kvm/devices/ |
| D | arm-vgic-v3.rst | 156 here is that of the latch which is set by ISPENDR and cleared by ICPENDR or
158 ISPENDR is the logical OR of the latch value and the input line level.
160 Raw access to the latch state is provided to userspace so that it can save
162 combination of the current input line level and the latch state, and cannot
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| /Documentation/devicetree/bindings/iio/dac/ |
| D | microchip,mcp4821.yaml | 51 Active Low LDAC (Latch DAC Input) pin used to update the DAC output.
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| /Documentation/virt/kvm/x86/ |
| D | timekeeping.rst | 139 0000 - Latch Timer 0 count for port 0x40
156 0100 - Latch Timer 1 count for port 0x41 - as described above
161 1000 - Latch Timer 2 count for port 0x42 - as described above
166 1101 - General counter latch
167 Latch combination of counters into corresponding ports
173 1110 - Latch timer status
174 Latch combination of counter mode into corresponding ports
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| /Documentation/locking/ |
| D | seqlock.rst | 144 Latch sequence counters (``seqcount_latch_t``)
147 Latch sequence counters are a multiversion concurrency control mechanism
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| /Documentation/devicetree/bindings/net/wireless/ |
| D | qcom,ath11k.yaml | 106 - description: misc-latch interrupt events
160 - const: misc-latch
324 "misc-latch",
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| /Documentation/input/devices/ |
| D | joystick-parport.rst | 92 NES and SNES pads have two input bits, Clock and Latch, which drive the
97 (pin 3) -----> Latch
128 | | | | | | +---------------> Latch
131 | +-------> Latch
137 | +-------> Latch | +---> Ground
145 | +----> Power | +----------> Latch
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pincfg-node.yaml | 31 description: latch weakly
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| D | marvell,armada-37xx-pinctrl.txt | 6 Inside this set of register the gpio latch allows exposing some
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| /Documentation/networking/device_drivers/hamradio/ |
| D | z8530drv.rst | 86 vector 0 # latch for interrupt vector
130 - address of the vector latch (aka "intack port") for PA0HZP
131 cards. There can be only one vector latch for all chips!
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| /Documentation/ABI/testing/ |
| D | sysfs-platform-mellanox-bootctl | 151 A successful write to this attribute will latch the
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| /Documentation/driver-api/ |
| D | mtdnand.rst | 908 /* Select the command latch by setting CLE to high */
910 /* Deselect the command latch by setting CLE to low */
912 /* Select the address latch by setting ALE to high */
914 /* Deselect the address latch by setting ALE to low */
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