Searched full:latency (Results 1 – 25 of 244) sorted by relevance
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| /Documentation/power/ |
| D | pm_qos_interface.rst | 10 * CPU latency QoS.
12 per-device latency constraints and PM QoS flags.
14 The latency unit used in the PM QoS framework is the microsecond (usec).
20 A global list of CPU latency QoS requests is maintained along with an aggregated
22 to the request list or elements of the list. For CPU latency QoS, the
32 Will insert an element into the CPU latency QoS list with the target value.
49 Returns the aggregated value for the CPU latency QoS.
53 CPU latency QoS list.
56 Adds a notification callback function to the CPU latency QoS. The callback is
57 called when the aggregated value for the CPU latency QoS is changed.
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| /Documentation/devicetree/bindings/power/ |
| D | domain-idle-state.yaml | 31 entry-latency-us:
33 The worst case latency in microseconds required to enter the idle
34 state. Note that, the exit-latency-us duration may be guaranteed only
35 after the entry-latency-us has passed.
37 exit-latency-us:
39 The worst case latency in microseconds required to exit the idle
59 - entry-latency-us
60 - exit-latency-us
71 entry-latency-us = <20>;
72 exit-latency-us = <40>;
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| /Documentation/devicetree/bindings/cache/ |
| D | baikal,bt1-l2-ctl.yaml | 27 baikal,l2-ws-latency:
29 description: Cycles of latency for Way-select RAM accesses
34 baikal,l2-tag-latency:
36 description: Cycles of latency for Tag RAM accesses
41 baikal,l2-data-latency:
43 description: Cycles of latency for Data RAM accesses
59 baikal,l2-ws-latency = <1>;
60 baikal,l2-tag-latency = <1>;
61 baikal,l2-data-latency = <2>;
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| D | l2c2x0.yaml | 69 arm,data-latency:
70 description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
72 without setup latency control should use a value of 0.
80 arm,tag-latency:
81 description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
82 read, write and setup latencies. Controllers without setup latency control
83 should use 0. Controllers without separate read and write Tag RAM latency
92 arm,dirty-latency:
93 description: Cycles of latency for Dirty RAMs. This is a single cell.
234 arm,data-latency = <1 1 1>;
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| /Documentation/devicetree/bindings/cpu/ |
| D | idle-states.yaml | 44 Idle state parameters (e.g. entry latency) are platform specific and need to
81 | latency |
83 | latency |
85 |<------- wakeup-latency ------->|
93 event conditions. The abort latency is assumed to be negligible
107 entry-latency: Worst case latency required to enter the idle state. The
108 exit-latency may be guaranteed only after entry-latency has passed.
113 wakeup-latency: Maximum delay between the signaling of a wake-up event and the
115 to be entry-latency + exit-latency.
127 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
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| /Documentation/arch/arm/omap/ |
| D | omap_pm.rst | 6 authors use these functions to communicate minimum latency or
17 latency framework or something else;
20 latency and throughput, rather than units which are specific to OMAP
34 1. Set the maximum MPU wakeup latency::
38 2. Set the maximum device wakeup latency::
42 3. Set the maximum system DMA transfer start latency (CORE pwrdm)::
88 latency, and the set_max_dev_wakeup_lat() function to constrain the
89 device wakeup latency (from clk_enable() to accessibility). For
92 /* Limit MPU wakeup latency */
96 /* Limit device powerdomain wakeup latency */
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| /Documentation/trace/ |
| D | timerlat-tracer.rst | 8 computes a *wakeup latency* value as the difference between the *current
34 # TASK-PID CPU# |||| TIMESTAMP ID CONTEXT LATENCY
47 prints two lines at every activation. The first is the *timer latency*
49 The second is the *timer latency* observed by the thread. The ACTIVATION
72 timer latency at the *irq* context higher than the configured
75 timer latency at the *thread* context is higher than the configured
98 In this case, the root cause of the timer latency does not point to a
119 clock latency latency
141 noise causes the major factor for the timer latency, because of preempt or
171 contribution to the *timer latency* and the stack trace, saved during
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| D | hwlat_detector.rst | 2 Hardware Latency Detector
14 kernel is highly latency sensitive.
24 The hardware latency detector works by hogging one of the cpus for configurable
40 redefine the threshold in microseconds (us) above which latency spikes will
74 - tracing_threshold - minimum latency value to be considered (usecs)
75 - tracing_max_latency - maximum hardware latency actually observed (usecs)
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| /Documentation/devicetree/bindings/opp/ |
| D | allwinner,sun50i-h6-operating-points.yaml | 49 clock-latency-ns: true
75 clock-latency-ns = <244144>; /* 8 32k periods */
84 clock-latency-ns = <244144>; /* 8 32k periods */
93 clock-latency-ns = <244144>; /* 8 32k periods */
109 clock-latency-ns = <244144>; /* 8 32k periods */
117 clock-latency-ns = <244144>; /* 8 32k periods */
126 clock-latency-ns = <244144>; /* 8 32k periods */
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| D | opp-v2.yaml | 62 clock-latency-ns = <300000>;
69 clock-latency-ns = <310000>;
74 clock-latency-ns = <290000>;
145 clock-latency-ns = <300000>;
152 clock-latency-ns = <310000>;
158 clock-latency-ns = <290000>;
225 clock-latency-ns = <300000>;
232 clock-latency-ns = <310000>;
238 clock-latency-ns = <290000>;
251 clock-latency-ns = <400000>;
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| D | opp-v2-kryo-cpu.yaml | 79 clock-latency-ns: true
217 clock-latency-ns = <200000>;
224 clock-latency-ns = <200000>;
231 clock-latency-ns = <200000>;
245 clock-latency-ns = <200000>;
252 clock-latency-ns = <200000>;
259 clock-latency-ns = <200000>;
266 clock-latency-ns = <200000>;
283 clock-latency-ns = <100000>;
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| /Documentation/admin-guide/pm/ |
| D | intel_uncore_frequency_scaling.rst | 23 Users may have some latency sensitive workloads where they do not want any
117 Efficiency vs. Latency Tradeoff
120 The Efficiency Latency Control (ELC) feature improves performance
122 optimize trade-off between latency and power consumption. For some
123 latency sensitive workloads further tuning can be done by SW to
147 Attributes for efficiency latency control:
150 This attribute is used to get/set the efficiency latency floor frequency.
155 This attribute is used to get/set the efficiency latency control low
159 This attribute is used to get/set the efficiency latency control high
163 This attribute is used to enable/disable the efficiency latency control
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| D | cpuidle.rst | 107 next wakeup event, or there are strict latency constraints preventing any of the
135 *exit latency*. The target residency is the minimum time the hardware must
140 latency, in turn, is the maximum time it will take a CPU asking the processor
142 wakeup from that state. Note that in general the exit latency also must cover
308 Then, the governor computes an extra latency limit to help "interactive"
309 workloads. It uses the observation that if the exit latency of the selected
315 of the extra latency limit is the predicted idle duration itself which
318 complete. The result of that division is compared with the latency limit coming
321 exit latency.
325 the predicted idle duration and the exit latency of it with the computed latency
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| /Documentation/tools/rtla/ |
| D | rtla-timerlat-top.rst | 5 Measures the operating system timer latency
46 automatic trace mode, instructing the tracer to stop if a *40 us* latency or
50 Timer Latency
51 0 00:00:12 | IRQ Timer Latency (us) | Thread Timer Latency (us)
79 IRQ latency: 28.13 us
104 Thread latency: 41.96 us (100%)
106 The system has exit from idle latency!
107 Max timerlat IRQ latency from idle: 17.48 us in cpu 4
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| D | common_timerlat_options.rst | 14 Stop trace if the *IRQ* latency is higher than the argument in us.
18 Stop trace if the *Thread* latency is higher than the argument in us.
22 Save the stack trace at the *IRQ* if a *Thread* latency is higher than the
29 **--dma-latency** *us*
31 *cyclictest* sets this value to *0* by default, use **--dma-latency** *0* to have
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| D | common_timerlat_description.rst | 5 debugging of operating system timer latency.
8 prints the timer latency at the timer *IRQ* handler and the *Thread*
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| /Documentation/networking/ |
| D | tcp-thin.rst | 13 on the data delivery latency, packet loss can be devastating for
25 In order to reduce application-layer latency when packets are lost,
26 a set of mechanisms has been made, which address these latency issues
50 "Improving latency for interactive, thin-stream applications over
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | nvidia,tegra124-cpufreq.txt | 17 - clock-latency: Specify the possible maximum transition latency for clock,
36 clock-latency = <300000>;
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| D | cpufreq-dt.txt | 17 - clock-latency: Specify the possible maximum transition latency for clock,
40 clock-latency = <61036>; /* two CLK32 periods */
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| D | apple,cluster-cpufreq.yaml | 77 clock-latency-ns = <7500>;
82 clock-latency-ns = <22000>;
93 clock-latency-ns = <8000>;
98 clock-latency-ns = <19000>;
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| D | cpufreq-spear.txt | 13 - clock-latency: Specify the possible maximum transition latency for clock, in
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| /Documentation/devicetree/bindings/thermal/ |
| D | thermal-idle.yaml | 38 exit-latency-us:
40 The exit latency constraint in microsecond for the injected idle state
41 for the device. It is the latency constraint to apply when selecting an
78 exit-latency-us = <500>;
94 exit-latency-us = <500>;
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| /Documentation/block/ |
| D | kyber-iosched.rst | 11 Target latency for reads (in nanoseconds).
15 Target latency for synchronous writes (in nanoseconds).
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| D | bfq-iosched.rst | 6 low-latency capabilities. In addition to cgroups support (blkio or io
10 low latency for time-sensitive applications, such as audio or video
16 In its default configuration, BFQ privileges latency over
17 throughput. So, when needed for achieving a lower latency, BFQ builds
20 throughput at all times, then do switch off all low-latency heuristics
23 latency and throughput, or on how to maximize throughput.
81 Low latency for interactive applications
102 Low latency for soft real-time applications
105 players/streamers, enjoy a low latency and a low drop rate, regardless
204 guaranteeing low latency or fairness. In these cases, overall
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| /Documentation/ABI/testing/ |
| D | debugfs-intel-iommu | 166 * 0 - disable sampling all latency data
168 * 1 - enable sampling IOTLB invalidation latency data
170 * 2 - enable sampling devTLB invalidation latency data
172 * 3 - enable sampling intr entry cache invalidation latency data
181 1) Disable sampling all latency data:
185 2) Enable sampling IOTLB invalidation latency data
207 3) Enable sampling devTLB invalidation latency data
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