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/Documentation/devicetree/bindings/pwm/
Dnxp,pca9685-pwm.txt1 NXP PCA9685 16-channel 12-bit PWM LED controller
5 - compatible: "nxp,pca9685-pwm"
6 - #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
12 - invert (bool): boolean to enable inverted logic
13 - open-drain (bool): boolean to configure outputs with open-drain structure;
14 if omitted use totem-pole structure
22 compatible = "nxp,pca9685-pwm";
23 #pwm-cells = <2>;
26 open-drain;
/Documentation/devicetree/bindings/leds/
Dnxp,pca963x.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP PCA963x LED controllers
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The NXP PCA963x are I2C-controlled LED drivers optimized for
14 Red/Green/Blue/Amber (RGBA) color mixing applications. Each LED is
19 - https://www.nxp.com/docs/en/data-sheet/PCA9632.pdf
20 - https://www.nxp.com/docs/en/data-sheet/PCA9633.pdf
21 - https://www.nxp.com/docs/en/data-sheet/PCA9634.pdf
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Dleds-aw2013.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-aw2013.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AWINIC AW2013 3-channel LED Driver
10 - Nikita Travkin <nikitos.tr@gmail.com>
13 The AW2013 is a 3-channel LED driver with I2C interface. It can control
14 LED brightness with PWM output.
25 description: Open-drain, low active interrupt pin "INTN".
26 Used to report completion of operations (power up, LED breath effects).
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/Documentation/driver-api/gpio/
Dintro.rst17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
39 other value (notably, "open drain" signaling).
41 - Input values are likewise readable (1, 0). Some chips support readback
42 of pins configured as "output", which is very useful in such "wire-OR"
44 input de-glitch/debounce logic, sometimes with software controls.
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Dboard.rst14 -----------
20 <function>-gpios, where <function> is the function the driver will request
26 led-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>, /* red */
30 power-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
33 Properties named <function>-gpio are also considered valid and old bindings use
38 "led" function, and GPIO 1 as the "power" GPIO::
42 red = gpiod_get_index(dev, "led", 0, GPIOD_OUT_HIGH);
43 green = gpiod_get_index(dev, "led", 1, GPIOD_OUT_HIGH);
44 blue = gpiod_get_index(dev, "led", 2, GPIOD_OUT_HIGH);
48 The led GPIOs will be active high, while the power GPIO will be active low (i.e.
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Dconsumer.rst21 - Simple compile coverage with e.g. COMPILE_TEST - it does not matter that
25 - Truly optional GPIOLIB support - where the driver does not really make use
26 of the GPIOs on certain compile-time configurations for certain systems, but
27 will use it under other compile-time configurations. In this case the
33 some open coding of error handling should be expected when you do this.
35 All the functions that work with the descriptor-based GPIO interface are
45 With the descriptor-based interface, GPIOs are identified with an opaque,
46 non-forgeable handler that must be obtained through a call to one of the
54 If a function is implemented by using several GPIOs together (e.g. a simple LED
62 see Documentation/driver-api/gpio/board.rst
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Ddriver.rst21 of a general purpose I/O. On the other hand a LED driver line may be used as a
26 between 0 and n-1, n being the number of GPIOs managed by the chip.
29 example if a system uses a memory-mapped set of I/O-registers where 32 GPIO
30 lines are handled by one bit per line in a 32-bit register, it makes sense to
44 So for example one platform could use global numbers 32-159 for GPIOs, with a
46 global numbers 0..63 with one set of GPIO controllers, 64-79 with another type
47 of GPIO controller, and on one particular board 80-95 with an FPGA. The legacy
49 2000-2063 to identify GPIO lines in a bank of I2C GPIO expanders.
60 - methods to establish GPIO line direction
61 - methods used to access GPIO line values
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/Documentation/devicetree/bindings/net/dsa/
Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
27 - enum:
28 - qca,qca8327
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/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-palmas.txt4 the configuration for Pull UP/DOWN, open drain etc.
7 - compatible: It must be one of following:
8 - "ti,palmas-pinctrl" for Palma series of the pincontrol.
9 - "ti,tps65913-pinctrl" for Palma series device TPS65913.
10 - "ti,tps80036-pinctrl" for Palma series device TPS80036.
12 Please refer to pinctrl-bindings.txt in this directory for details of the
19 those pin(s), and various pin configuration parameters, such as pull-up,
20 open drain.
32 - ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode.
35 - ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode.
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Dnvidia,tegra234-pinmux-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 $ref: nvidia,tegra-pinmux-common.yaml
23 dmic3, led, vi0_alt, i2s5, nv, extperiph3, extperiph4, spi4,
33 nvidia,enable-input: true
34 nvidia,open-drain: true
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Dlantiq,pinctrl-falcon.txt4 - compatible: "lantiq,pinctrl-falcon"
5 - reg: Should contain the physical address and length of the gpio/pinmux
8 Please refer to pinctrl-bindings.txt in this directory for details of the
16 pull-up and open-drain
31 Required subnode-properties:
32 - lantiq,groups : An array of strings. Each string contains the name of a group.
34 - lantiq,function: A string containing the name of the function to mux to the
44 rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm
49 Required subnode-properties:
50 - lantiq,pins : An array of strings. Each string contains the name of a pin.
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/Documentation/devicetree/bindings/mfd/
Drohm,bd71828-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71828-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
13 BD71828GW is a single-chip power management IC for battery-powered portable
15 single-cell linear charger. Also included is a Coulomb counter, a real-time
21 - const: rohm,bd71828
23 - items:
24 - const: rohm,bd71879
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Drohm,bd71815-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71815-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
13 BD71815AGW is a single-chip power management ICs for battery-powered
15 for LED and a 500 mA single-cell linear charger. Also included is a Coulomb
16 counter, a real-time clock (RTC), and a 32.768 kHz clock gate and two GPOs.
30 gpio-controller: true
32 "#gpio-cells":
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/Documentation/devicetree/bindings/input/
Dmicrochip,cap11xx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Microchip CAP1xxx Family of RightTouchTM multiple-channel capacitive
11 touch controllers and LED drivers. The device communication via I2C only.
14 - Rob Herring <robh@kernel.org>
19 - microchip,cap1106
20 - microchip,cap1126
21 - microchip,cap1188
22 - microchip,cap1203
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/Documentation/devicetree/bindings/gpio/
Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
39 such as if the consumer desire the line to be active low (inverted) or open
40 drain. This is the recommended practice.
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/Documentation/scsi/
Dsym53c8xx_2.rst1 .. SPDX-License-Identifier: GPL-2.0
4 SYM-2 driver
11 95170 DEUIL LA BARRE - FRANCE
15 2004-10-09
43 10.2.3 LED support
67 This driver supports the whole SYM53C8XX family of PCI-SCSI controllers.
68 It also support the subset of LSI53C10XX PCI-SCSI controllers that are based
72 with the FreeBSD SYM-2 driver. The 'glue' that allows this driver to work
81 - Wolfgang Stanglmeier <wolf@cologne.de>
82 - Stefan Esser <se@mi.Uni-Koeln.de>
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Dncr53c8xx.rst1 .. SPDX-License-Identifier: GPL-2.0
11 95170 DEUIL LA BARRE - FRANCE
52 10.2.12 LED support
64 10.4 PCI configuration fix-up boot option
81 16.1 Synchronous timings for 53C875 and 53C860 Ultra-SCSI controllers
82 16.2 Synchronous timings for fast SCSI-2 53C8XX controllers
97 - Gerard Roudier <groudier@free.fr>
101 - Wolfgang Stanglmeier <wolf@cologne.de>
102 - Stefan Esser <se@mi.Uni-Koeln.de>
106 - ncr53c8xx generic driver that supports all the SYM53C8XX family including
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/Documentation/admin-guide/
Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
41 If set to vendor, prefer vendor-specific driver
73 Documentation/firmware-guide/acpi/debug.rst for more information about
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