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/Documentation/devicetree/bindings/interrupt-controller/
Dloongson,liointc.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
28 - loongson,liointc-1.0
29 - loongson,liointc-1.0a
30 - loongson,liointc-2.0
66 If a CPU interrupt line didn't connect with liointc, then keep its
89 - loongson,liointc-2.0
108 compatible = "loongson,liointc-1.0";
Dloongson,htvec.yaml51 interrupt-parent = <&liointc>;
Dloongson,htpic.yaml55 interrupt-parent = <&liointc>;
/Documentation/arch/loongarch/
Dirq-chip-model.rst9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
25 to LIOINTC, and then CPUINTC::
33 | LIOINTC | <-- | UARTs |
60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
70 | EIOINTC | | LIOINTC | <-- | UARTs |
92 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
102 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
129 LIOINTC::
[all …]
/Documentation/translations/zh_TW/arch/loongarch/
Dirq-chip-model.rst13 中的中斷控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
18 CPUINTC是一種CPU內部的每個核本地的中斷控制器，LIOINTC/EIOINTC/HTVECINTC是CPU內部的
36 | LIOINTC | <-- | UARTs |
72 | EIOINTC | | LIOINTC | <-- | UARTs |
99 LIOINTC::
153 - LIOINTC：即《龍芯3A5000處理器使用手冊》第11.1節所描述的“傳統I/O中斷”；
/Documentation/translations/zh_CN/arch/loongarch/
Dirq-chip-model.rst13 中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
18 CPUINTC是一种CPU内部的每个核本地的中断控制器，LIOINTC/EIOINTC/HTVECINTC是CPU内部的
36 | LIOINTC | <-- | UARTs |
72 | EIOINTC | | LIOINTC | <-- | UARTs |
104 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
131 LIOINTC::
185 - LIOINTC：即《龙芯3A5000处理器使用手册》第11.1节所描述的“传统I/O中断”；