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/Documentation/devicetree/bindings/net/
Dengleder,tsnep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TSN endpoint Ethernet MAC
10 - Gerhard Engleder <gerhard@engleder-embedded.com>
13 - $ref: ethernet-controller.yaml#
26 interrupt-names:
29 - const: mac
30 - const: txrx-1
31 - const: txrx-2
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Dcavium-pip.txt10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
27 - #address-cells: Must be <1>.
29 - #size-cells: Must be <0>.
32 - compatible: "cavium,octeon-3860-pip-port"
36 - reg: The port number within the interface group.
[all …]
Dasix,ax88178.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Oleksij Rempel <o.rempel@pengutronix.de>
16 - $ref: ethernet-controller.yaml#
21 - enum:
22 - usbb95,1720 # ASIX AX88172
23 - usbb95,172a # ASIX AX88172A
24 - usbb95,1780 # ASIX AX88178
25 - usbb95,7720 # ASIX AX88772
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Ddavicom,dm9051.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Joseph CHANG <josright123@gmail.com>
13 The DM9051 is a fully integrated and cost-effective low pin count single
17 - $ref: ethernet-controller.yaml#
26 spi-max-frequency:
32 local-mac-address: true
34 mac-address: true
37 - compatible
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Dqca,qca7000.txt3 The QCA7000 is a serial-to-powerline bridge with a host interface which could
13 - compatible : Should be "qca,qca7000"
14 - reg : Should specify the SPI chip select
15 - interrupts : The first cell should specify the index of the source
18 - spi-cpha : Must be set
19 - spi-cpol : Must be set
22 - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at.
26 - qca,legacy-mode : Set the SPI data transfer of the QCA7000 to legacy mode.
33 The MAC address will be determined using the optional properties
40 #address-cells = <1>;
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Dasix,ax88796c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Łukasz Stelmach <l.stelmach@samsung.com>
18 ../spi/spi-controller.yaml must be specified.
21 - $ref: ethernet-controller.yaml#
22 - $ref: /schemas/spi/spi-peripheral-props.yaml
31 spi-max-frequency:
37 reset-gpios:
43 controller-data: true
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Dmicrochip,lan95xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Oleksij Rempel <o.rempel@pengutronix.de>
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - usb424,9500 # SMSC9500 USB Ethernet Device
24 - usb424,9505 # SMSC9505 USB Ethernet Device
25 - usb424,9530 # SMSC LAN9530 USB Ethernet Device
26 - usb424,9730 # SMSC LAN9730 USB Ethernet Device
[all …]
Dopencores-ethoc.txt1 * OpenCores MAC 10/100 Mbps
4 - compatible: Should be "opencores,ethoc".
5 - reg: two memory regions (address and length),
8 - interrupts: interrupt for the device.
11 - clocks: phandle to refer to the clk used as per
12 Documentation/devicetree/bindings/clock/clock-bindings.txt
20 local-mac-address = [00 50 c2 13 6f 00];
Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
21 Specifies the MAC address that was assigned to the network device.
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
28 Specifies the MAC address that was last used by the boot
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Dxlnx,emaclite.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
11 - Harini Katakam <harini.katakam@amd.com>
14 - $ref: ethernet-controller.yaml#
19 - xlnx,opb-ethernetlite-1.01.a
20 - xlnx,opb-ethernetlite-1.01.b
21 - xlnx,xps-ethernetlite-1.00.a
22 - xlnx,xps-ethernetlite-2.00.a
[all …]
Dmicrochip,lan8650.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN8650/1 10BASE-T1S MACPHY Ethernet Controllers
10 - Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
13 The LAN8650/1 combines a Media Access Controller (MAC) and an Ethernet
15 (MAC) module implements a 10 Mbps half duplex Ethernet MAC, compatible
16 with the IEEE 802.3 standard and a 10BASE-T1S physical layer transceiver
18 the MAC-PHY is specified in the OPEN Alliance 10BASE-T1x MACPHY Serial
22 - $ref: /schemas/net/ethernet-controller.yaml#
[all …]
Dadi,adin1110.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ADI ADIN1110 MAC-PHY
10 - Alexandru Tachici <alexandru.tachici@analog.com>
13 The ADIN1110 is a low power single port 10BASE-T1L MAC-
15 an Ethernet PHY core with a MAC and all the associated analog
18 The ADIN2111 is a low power, low complexity, two-Ethernet ports
19 switch with integrated 10BASE-T1L PHYs and one serial peripheral
22 with the IEEE 802.3cg-2019 Ethernet standard for long reach
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Dlitex,liteeth.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Joel Stanley <joel@jms.id.au>
17 https://github.com/enjoy-digital/liteeth/.
20 - $ref: ethernet-controller.yaml#
28 - description: MAC registers
29 - description: MDIO registers
30 - description: Packet buffer
32 reg-names:
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Dapm-xgene-enet.txt1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
[all …]
Dmicrochip,lan78xx.txt8 - compatible: Should be one of "usb424,7800", "usb424,7801" or "usb424,7850".
10 The MAC address will be determined using the optional properties
14 - microchip,led-modes: a 0..4 element vector, with each element configuring
16 are defined in "include/dt-bindings/net/microchip-lan78xx.h".
22 usb-port@1 {
25 #address-cells = <1>;
26 #size-cells = <0>;
28 usb-port@1 {
31 #address-cells = <1>;
32 #size-cells = <0>;
[all …]
Dsocionext,uniphier-ave4.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/socionext,uniphier-ave4.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro4-ave4
20 - socionext,uniphier-pxs2-ave4
21 - socionext,uniphier-ld11-ave4
22 - socionext,uniphier-ld20-ave4
23 - socionext,uniphier-pxs3-ave4
[all …]
Dmarvell-orion-net.txt12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
23 - #address-cells: shall be 1.
24 - #size-cells: shall be 0.
25 - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth".
26 - reg: address and length of the controller registers.
29 - clocks: phandle reference to the controller clock.
30 - marvell,tx-checksum-limit: max tx packet size for hardware checksum.
35 - compatible: shall be one of "marvell,orion-eth-port",
36 "marvell,kirkwood-eth-port".
[all …]
Dhisilicon-hns-nic.txt4 - compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
5 "hisilicon,hns-nic-v1" is for hip05.
6 "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
7 - ae-handle: accelerator engine handle for hns,
9 see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
17 port-id can be 2 to 7. Here is the diagram:
18 +-----+---------------+
20 +-+-+-+---+-+-+-+-+-+-+
24 (0,1) (2-7)
[all …]
Ddavinci_emac.txt7 - compatible: "ti,davinci-dm6467-emac", "ti,am3517-emac" or
8 "ti,dm816-emac"
9 - reg: Offset and length of the register set for the device
10 - ti,davinci-ctrl-reg-offset: offset to control register
11 - ti,davinci-ctrl-mod-reg-offset: offset to control module register
12 - ti,davinci-ctrl-ram-offset: offset to control module ram
13 - ti,davinci-ctrl-ram-size: size of control module ram
14 - interrupts: interrupt mapping for the davinci emac interrupts sources:
21 - phy-handle: See ethernet.txt file in the same directory.
23 - ti,davinci-rmii-en: 1 byte, 1 means use RMII
[all …]
Daltr,tse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera Triple Speed Ethernet MAC driver (TSE)
10 - Maxime Chevallier <maxime.chevallier@bootlin.com>
15 - const: altr,tse-1.0
16 - const: ALTR,tse-1.0
18 - const: altr,tse-msgdma-1.0
23 interrupt-names:
25 - const: rx_irq
[all …]
Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
/Documentation/networking/
Dnet_failover.rst1 .. SPDX-License-Identifier: GPL-2.0
17 a passthru/vf device with the same MAC gets registered as 'primary' slave
28 virtio-net accelerated datapath: STANDBY mode
31 net_failover enables hypervisor controlled accelerated datapath to virtio-net
35 feature on the virtio-net interface and assign the same MAC address to both
36 virtio-net and VF interfaces.
42 <mac address='52:54:00:00:12:53'/>
49 <alias name='ua-backup0'/>
52 <mac address='52:54:00:00:12:53'/>
54 <address type='pci' domain='0x0000' bus='0x42' slot='0x02' function='0x5'/>
[all …]
Dnetconsole.rst1 .. SPDX-License-Identifier: GPL-2.0
29 It can be used either built-in or as a module. As a built-in,
41 netconsole=[+][r][src-port]@[src-ip]/[<dev>],[tgt-port]@<tgt-ip>/[tgt-macaddr]
46 src-port source for UDP packets (defaults to 6665)
47 src-ip source IP to use (interface address)
49 tgt-port port for logging agent (6666)
50 tgt-ip IP address for logging agent
51 tgt-macaddr ethernet MAC address for logging agent (broadcast)
71 Built-in netconsole starts immediately after the TCP stack is
73 address.
[all …]
Dbonding.rst1 .. SPDX-License-Identifier: GPL-2.0
11 Corrections, HA extensions: 2000/10/03-15:
13 - Willy Tarreau <willy at meta-x.org>
14 - Constantine Gavrilov <const-g at xpert.com>
15 - Chad N. Tindel <ctindel at ieee dot org>
16 - Janice Girouard <girouard at us dot ibm dot com>
17 - Jay Vosburgh <fubar at us dot ibm dot com>
22 - Mitch Williams <mitch.a.williams at intel.com>
35 the original tools from extreme-linux and beowulf sites will not work
119 -----------------------------------------------
[all …]
/Documentation/networking/devlink/
Ddevlink-dpipe.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ``devlink-dpipe`` provides a standardized way to provide visibility into the
34 Level Path Compression trie (LPC-trie) in hardware.
45 The ``devlink-dpipe`` interface closes this gap. The hardware's pipeline is
50 configuration, but the ``devlink-dpipe`` interface uses it for visibility
52 ``devlink-dpipe`` should change according to the changes done by the
84 ``devlink-dpipe`` generally is not intended for configuration. The exception
96 -----
107 ------------
113 and should be defined in the driver. Additionally, each driver-specific
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