Searched full:lpc (Results 1 – 25 of 32) sorted by relevance
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| /Documentation/devicetree/bindings/mfd/ |
| D | aspeed-lpc.yaml | 5 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
8 title: Aspeed Low Pin Count (LPC) Bus Controller
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
17 primary use case of the Aspeed LPC controller is as a slave on the bus
21 The LPC controller is represented as a multi-function device to account for the
26 * An LPC Host Interface Controller manages functions exposed to the host such
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
34 Additionally the state of the LPC controller influences the pinmux
42 - aspeed,ast2400-lpc-v2
43 - aspeed,ast2500-lpc-v2
[all …]
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| /Documentation/devicetree/bindings/rtc/ |
| D | rtc-st-lpc.txt | 1 STMicroelectronics Low Power Controller (LPC) - RTC
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Must be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
23 lpc@fde05000 {
24 compatible = "st,stih407-lpc";
[all …]
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| /Documentation/devicetree/bindings/timer/ |
| D | st,stih407-lpc | 1 STMicroelectronics Low Power Controller (LPC) - Clocksource
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../rtc/rtc-st-lpc.txt for RTC options]
12 - compatible : Must be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
23 lpc@fde05000 {
24 compatible = "st,stih407-lpc";
[all …]
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| /Documentation/devicetree/bindings/watchdog/ |
| D | st_lpc_wdt.txt | 1 STMicroelectronics Low Power Controller (LPC) - Watchdog
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
7 [See: ../rtc/rtc-st-lpc.txt for RTC options]
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Should be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
33 lpc@fde05000 {
[all …]
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| /Documentation/devicetree/bindings/ipmi/ |
| D | aspeed,ast2400-kcs-bmc.yaml | 14 interfaces on the LPC bus for in-band IPMI communication with their host.
43 aspeed,lpc-io-reg:
48 The host CPU LPC IO data and status addresses for the device. For most
52 aspeed,lpc-interrupts:
57 A 2-cell property expressing the LPC SerIRQ number and the interrupt
67 description: The LPC channel number in the controller
95 - aspeed,lpc-io-reg
103 aspeed,lpc-io-reg = <0xca2>;
104 aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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| D | npcm7xx-kcs-bmc.txt | 17 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
|
| /Documentation/devicetree/bindings/arm/hisilicon/ |
| D | low-pin-count.yaml | 13 Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which
17 LPC device node.
28 - hisilicon,hip06-lpc
29 - hisilicon,hip07-lpc
50 compatible = "hisilicon,hip06-lpc";
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| /Documentation/ABI/stable/ |
| D | sysfs-driver-aspeed-vuart | 5 will appear on the host <-> BMC LPC bus.
13 the UART will appear on the host <-> BMC LPC bus.
21 host via the BMC LPC bus.
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| /Documentation/translations/zh_TW/arch/loongarch/ |
| D | irq-chip-model.rst | 16 斷控制器）、PCH-LPC（LS7A芯片組的LPC中斷控制器）和PCH-MSI（MSI中斷控制器）。
19 全局中斷控制器（每個芯片一個，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
28 PCH-LPC/PCH-MSI，然後被HTVECINTC統一收集，再發送到LIOINTC，最後到達CPUINTC::
51 | PCH-LPC | | Devices | | Devices |
64 PCH-LPC/PCH-MSI，然後被EIOINTC統一收集，再直接到達CPUINTC::
82 | PCH-LPC | | Devices | | Devices |
129 PCH-LPC::
157 - PCH-LPC：即《龍芯7A1000橋片用戶手冊》第24.3節所描述的“LPC中斷”。
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| /Documentation/translations/zh_CN/arch/loongarch/ |
| D | irq-chip-model.rst | 16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
51 | PCH-LPC | | Devices | | Devices |
64 PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC::
82 | PCH-LPC | | Devices | | Devices |
95 送达CPUINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/PCH-LPC，然后由EIOINTC
114 | Devices | | PCH-LPC | | Devices |
161 PCH-LPC::
189 - PCH-LPC：即《龙芯7A1000桥片用户手册》第24.3节所描述的“LPC中断”。
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| /Documentation/arch/loongarch/ |
| D | irq-chip-model.rst | 11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
48 | PCH-LPC | | Devices | | Devices |
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
80 | PCH-LPC | | Devices | | Devices |
94 go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::
112 | Devices | | PCH-LPC | | Devices |
159 PCH-LPC::
191 - PCH-LPC is "LPC Interrupts" described in Section 24.3 of
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| /Documentation/devicetree/bindings/serial/ |
| D | 8250.yaml | 18 - aspeed,lpc-io-reg
20 - aspeed,lpc-interrupts
202 configured. One possible data source is the LPC/eSPI mode bit. Only
206 aspeed,lpc-io-reg:
210 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
212 aspeed,lpc-interrupts:
260 aspeed,lpc-io-reg = <0x3f8>;
261 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
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| /Documentation/devicetree/bindings/soc/aspeed/ |
| D | uart-routing.yaml | 44 lpc: lpc@1e789000 {
45 compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
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| /Documentation/devicetree/bindings/net/ |
| D | lpc-eth.txt | 4 - compatible: Should be "nxp,lpc-eth"
21 compatible = "nxp,lpc-eth";
|
| /Documentation/devicetree/bindings/tpm/ |
| D | tcg,tpm-tis-mmio.yaml | 15 one of them being LPC (via MMIO). The standard is named:
|
| /Documentation/core-api/ |
| D | dma-isa-lpc.rst | 2 DMA with ISA and LPC devices
8 controller. Even though ISA is more or less dead today the LPC bus
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| D | index.rst | 108 dma-isa-lpc
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| /Documentation/translations/zh_CN/core-api/ |
| D | index.rst | 122 dma-isa-lpc
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | aspeed,ast2600-pinctrl.yaml | 105 - LPC
331 - LPC
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| D | nuvoton,npcm845-pinctrl.yaml | 83 r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
106 pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
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| D | aspeed,ast2500-pinctrl.yaml | 38 1: compatible with "aspeed,ast2500-lpc", "syscon"
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| /Documentation/devicetree/bindings/clock/ |
| D | lpc1850-ccu.txt | 36 specific LPC part. Check the user manual for your specific part.
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| D | lpc1850-cgu.txt | 42 specific LPC part. Base clocks are numbered from 0 to 27.
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| /Documentation/i2c/busses/ |
| D | i2c-sis630.rst | 52 LPC Controller (rev 36)
|
| /Documentation/accel/ |
| D | introduction.rst | 110 * `LPC 2022 Accelerators BOF outcomes summary <https://airlied.blogspot.com/2022/09/accelerators-bo…
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