Searched full:manager (Results 1 – 25 of 221) sorted by relevance
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,apr-services.yaml | 24 5 = Voice Stream Manager Service.
25 6 = Voice processing manager.
26 7 = Audio Stream Manager Service.
27 8 = Audio Device Manager Service.
28 9 = Multimode voice manager.
31 12 = Ultrasound stream manager.
32 13 = Listen stream manager.
34 1 = Audio Process Manager Service
35 2 = Proxy Resource Manager Service.
37 4 = Voice processing manager.
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| D | qcom,saw2.yaml | 7 title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2)
14 The Qualcomm Subsystem Power Manager is used to control the peripheral logic
17 The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
85 saw0: power-manager@f9089000 {
96 power-manager@17812000 {
101 power-manager@17912000 {
110 power-manager@2089000 {
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| /Documentation/power/ |
| D | charger-manager.rst | 2 Charger Manager
7 Charger Manager provides in-kernel battery charger management that
12 Charger Manager is a platform_driver with power-supply-class entries.
13 An instance of Charger Manager (a platform-device created with Charger-Manager)
16 the system may need multiple instances of Charger Manager.
21 Charger Manager supports the following:
43 Charger Manager provides a function "cm_suspend_again" that can be
48 that are used by Charger Manager.
60 2. Global Charger-Manager Data related with suspend_again
62 In order to setup Charger Manager with suspend-again feature
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| /Documentation/devicetree/bindings/misc/ |
| D | intel,ixp4xx-ahb-queue-manager.yaml | 5 $id: http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#
8 title: Intel IXP4xx AHB Queue Manager
14 The IXP4xx AHB Queue Manager maintains queues as circular buffers in
18 queues from the queue manager with foo-queue = <&qmgr N> where the
19 &qmgr is a phandle to the queue manager and N is the queue resource
26 - const: intel,ixp4xx-ahb-queue-manager
47 qmgr: queue-manager@60000000 {
48 compatible = "intel,ixp4xx-ahb-queue-manager";
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| D | xlnx,tmr-manager.yaml | 4 $id: http://devicetree.org/schemas/misc/xlnx,tmr-manager.yaml#
7 title: Xilinx Triple Modular Redundancy(TMR) Manager IP
13 The Triple Modular Redundancy(TMR) Manager is responsible for handling the
21 - xlnx,tmr-manager-1.0
43 tmr-manager@44a10000 {
44 compatible = "xlnx,tmr-manager-1.0";
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| /Documentation/devicetree/bindings/mailbox/ |
| D | ti,message-manager.txt | 1 Texas Instruments' Message Manager Driver
4 The Texas Instruments' Message Manager is a mailbox controller that has
6 manager is broken up into queues in different address regions that are called
10 Message Manager Device Node:
14 - compatible: Shall be: "ti,k2g-message-manager"
24 For ti,k2g-message-manager, this shall contain:
33 compatible = "ti,k2g-message-manager";
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| /Documentation/devicetree/bindings/firmware/ |
| D | gunyah-hypervisor.yaml | 15 of the message queues used to communicate with the Gunyah Resource Manager.
16 …See also: https://github.com/quic/gunyah-resource-manager/blob/develop/src/vm_creation/dto_constru…
35 Resource Manager node which is required to communicate to Resource
36 Manager VM using Gunyah Message Queues.
40 const: gunyah-resource-manager
76 compatible = "gunyah-resource-manager";
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| /Documentation/virt/gunyah/ |
| D | index.rst | 86 Capabilities which are typically never given out by the Resource Manager (RM).
91 Resource Manager
94 The Gunyah Resource Manager (RM) is a privileged application VM supporting the
96 system. The resource manager can be treated as an extension of the Hypervisor
99 the platform. The resource manager runs at arm64 NS-EL1, similar to other
102 Communication with the resource manager from other virtual machines happens as
118 The source for the resource manager is available at
119 https://github.com/quic/gunyah-resource-manager.
121 The resource manager provides the following features:
130 manager. This is provided to VMs via a 'hypervisor' device tree node which is
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| /Documentation/devicetree/bindings/power/supply/ |
| D | sbs,sbs-manager.yaml | 4 $id: http://devicetree.org/schemas/power/supply/sbs,sbs-manager.yaml#
7 title: SBS compliant manager
22 - sbs,sbs-manager
24 - const: sbs,sbs-manager
66 batman: battery-manager@a {
67 compatible = "lltc,ltc1760", "sbs,sbs-manager";
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| D | charger-manager.yaml | 4 $id: http://devicetree.org/schemas/power/supply/charger-manager.yaml#
7 title: Charger Manager
13 Binding for the legacy charger manager driver.
18 const: charger-manager
33 description: name of the charger manager
172 charger-manager {
173 compatible = "charger-manager";
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| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
8 - compatible : Should be "altr,socfpga-ecc-manager"
33 compatible = "altr,socfpga-ecc-manager";
52 Arria10 SoCFPGA ECC Manager
53 The Arria10 SoC ECC Manager handles the IRQs for each peripheral
58 - compatible : Should be "altr,socfpga-a10-ecc-manager"
59 - altr,sysgr-syscon : phandle to Arria10 System Manager Block
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| /Documentation/driver-api/fpga/ |
| D | fpga-mgr.rst | 1 FPGA Manager
7 The FPGA manager core exports a set of functions for programming an FPGA with
11 it's just binary data. The FPGA manager core won't parse it.
26 To add another FPGA manager, write a driver that implements a set of ops. The
53 mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",
123 API for implementing a new FPGA Manager driver
127 * struct fpga_manager - the FPGA manager struct
128 * struct fpga_manager_ops - Low level FPGA manager driver ops
130 * __fpga_mgr_register_full() - Create and register an FPGA manager using the
132 * __fpga_mgr_register() - Create and register an FPGA manager using standard
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| D | fpga-programming.rst | 8 FPGA manager, bridge, and regions. The actual function used to
12 the FPGA manager and bridges. It will:
15 * lock the mutex of the region's FPGA manager
29 When the FPGA region driver probed, it was given a pointer to an FPGA manager
30 driver so it knows which manager to use. The region also either has a list of
95 FPGA Manager flags
98 :doc: FPGA Manager flags
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| D | fpga-region.rst | 12 an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
24 * which FPGA manager to use to do the programming
60 Manager it will be using to do the programming. This usually would happen
63 * fpga_mgr_get() - Get a reference to an FPGA manager, raise ref count
64 * of_fpga_mgr_get() - Get a reference to an FPGA manager, raise ref count,
66 * fpga_mgr_put() - Put an FPGA manager
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| /Documentation/devicetree/bindings/fpga/ |
| D | xlnx,pr-decoupler.yaml | 7 title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
21 Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager Softcore
23 eXchange AXI shutdown manager prevents AXI traffic from passing through the
38 - const: xlnx,dfx-axi-shutdown-manager-1.00
39 - const: xlnx,dfx-axi-shutdown-manager
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| D | altera-socfpga-fpga-mgr.txt | 1 Altera SOCFPGA FPGA Manager
6 - The first index is for FPGA manager register access.
8 - interrupts : interrupt for the FPGA Manager device.
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| D | fpga-region.yaml | 73 * In some implementations, the FPGA Manager transparently handles gating the
79 FPGA Manager
80 * An FPGA Manager is a hardware block that programs an FPGA under the control
119 2. Program the FPGA using the FPGA manager.
135 * FPGA Manager
151 reconfiguration. It must include a phandle to an FPGA Manager. The base
162 If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA
163 Manager specified by its ancestor FPGA Region. This supports both the case
164 where the same FPGA Manager is used for all of an FPGA as well the case where
165 a different FPGA Manager is used for each region.
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| D | altera-socfpga-a10-fpga-mgr.txt | 1 Altera SOCFPGA Arria10 FPGA Manager
6 - The first index is for FPGA manager register access.
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| /Documentation/ABI/testing/ |
| D | sysfs-class-fpga-manager | 5 Description: Name of low level fpga manager driver.
11 Description: Read fpga manager state as a string.
18 This is a superset of FPGA states and fpga manager driver
19 states. The fpga manager driver is walking through these steps
42 Description: Read fpga manager status as a string.
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| /Documentation/devicetree/bindings/net/pse-pd/ |
| D | microchip,pd692x0.yaml | 29 List of the PD69208T4/PD69204T4/PD69208M PSE managers. Each manager
36 physical ports available on a manager have to be described in the
51 "^manager@[0-9a-b]$":
55 PD69208T4/PD69204T4/PD69208M PSE manager exposing 4 or 8 physical
61 Incremental index of the PSE manager starting from 0, ranging
109 manager@0 {
131 manager@1 {
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| /Documentation/devicetree/bindings/power/ |
| D | qcom,kpss-acc-v2.yaml | 13 The KPSS ACC provides clock, power manager, and reset control to a Krait CPU.
17 power-manager for enabling the cpu.
37 power-manager@f9088000 {
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| /Documentation/admin-guide/device-mapper/ |
| D | persistent-data.rst | 31 The block manager
34 dm-block-manager.[hc]
42 The transaction manager
45 dm-transaction-manager.[hc]
49 transaction manager is by shadowing an existing block (ie. doing
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| /Documentation/admin-guide/mm/ |
| D | userfaultfd.rst | 43 passed using unix domain sockets to a manager process, so the same
44 manager process could handle the userfaults of a multitude of
47 themselves on the same region the manager is already tracking, which
366 When the ``userfaultfd`` is monitored by an external manager, the manager
368 layout. Userfaultfd can notify the manager about such changes using
370 manager has to explicitly enable these events by setting appropriate
376 duplicated into the newly created process. The manager
383 different location, the manager will receive
394 enable notifications about memory unmapping. The manager will
400 ``userfaultfd`` manager. In the former case, the virtual memory is
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| /Documentation/devicetree/bindings/arm/altera/ |
| D | socfpga-clk-manager.yaml | 4 $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
7 title: Altera SOCFPGA Clock Manager
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| D | socfpga-system.txt | 1 Altera SOCFPGA System Manager
19 for system manager register.
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