Searched full:mapped (Results 1 – 25 of 514) sorted by relevance
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| /Documentation/devicetree/bindings/gpio/ |
| D | xylon,logicvc-gpio.yaml | 19 which are mapped by the driver as follows:
20 - GPIO[4:0] (display control) mapped to index 0-4
21 - EN_BLIGHT (power control) mapped to index 5
22 - EN_VDD (power control) mapped to index 6
23 - EN_VEE (power control) mapped to index 7
24 - V_EN (power control) mapped to index 8
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| D | gpio-mm-lantiq.txt | 1 Lantiq SoC External Bus memory mapped GPIO controller
7 The node describing the memory mapped GPIOs needs to be a child of the node
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| /Documentation/userspace-api/media/dvb/ |
| D | dmx-munmap.rst | 31 Address of the mapped buffer as returned by the
35 Length of the mapped buffer. This must be the same value as given to
41 Unmaps a previously with the :c:func:`mmap()` function mapped
52 mapped yet.
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| D | dmx-reqbufs.rst | 36 This ioctl is used to initiate a memory mapped or DMABUF based demux I/O.
38 Memory mapped buffers are located in device memory and must be allocated
39 with this ioctl before they can be mapped into the application's address
63 buffers, however this cannot succeed when any buffers are still mapped.
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| D | dmx-mmap.rst | 49 The ``flags`` parameter specifies the type of the mapped object,
50 mapping options and whether modifications made to the mapped copy of
61 ``MAP_SHARED`` allows applications to share the mapped memory with
94 On success :c:func:`mmap()` returns a pointer to the mapped buffer. On
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| /Documentation/userspace-api/media/v4l/ |
| D | func-munmap.rst | 29 Address of the mapped buffer as returned by the
33 Length of the mapped buffer. This must be the same value as given to
43 Unmaps a previously with the :c:func:`mmap()` function mapped
54 mapped yet.
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| D | colorspaces-defs.rst | 147 - For the Hue, the 360 degrees are mapped into 8 bits, i.e. each
168 mapped to [0…255] (with possible clipping to [1…254] to avoid the
169 0x00 and 0xff values). Cb and Cr are mapped from [-0.5…0.5] to
174 is mapped to [16…235]. Cb and Cr are mapped from [-0.5…0.5] to
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| D | func-mmap.rst | 64 The ``flags`` parameter specifies the type of the mapped object,
65 mapping options and whether modifications made to the mapped copy of
76 ``MAP_SHARED`` allows applications to share the mapped memory with
116 On success :c:func:`mmap()` returns a pointer to the mapped buffer. On
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| D | mmap.rst | 36 the allocated memory, provided none of the buffers are still mapped.
48 multi-planar API, every plane of every buffer has to be mapped
115 the buffers mapped so far. */
184 /* Every plane has to be mapped separately */
195 the buffers and planes mapped so far. */
224 Initially all mapped buffers are in dequeued state, inaccessible by the
226 mapped buffers, then to start capturing and enter the read loop. Here
236 ioctl. The status of a buffer being mapped, enqueued, full or empty can
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| /Documentation/mm/ |
| D | vmalloced-kernel-stacks.rst | 4 Virtually Mapped Kernel Stack Support
15 series that introduced the `Virtually Mapped Kernel Stacks feature
25 Virtually mapped kernel stacks with guard pages cause kernel stack
30 support for virtually mapped stacks with guard pages. This feature
42 Architectures that can support Virtually Mapped Kernel Stacks should
61 mapped task stacks. This option depends on HAVE_ARCH_VMAP_STACK.
63 - Enable this if you want the use virtually-mapped kernel stacks
88 pages are mapped into contiguous kernel virtual space with PAGE_KERNEL
114 virtually mapped kernel stacks are enabled.
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| /Documentation/devicetree/bindings/display/ |
| D | st,stih4xx.txt | 6 - reg: Physical base address of the IP registers and length of memory mapped region.
14 - reg: Physical base address of the IP registers and length of memory mapped region.
32 - reg: Physical base address of the IP registers and length of memory mapped region.
48 - reg: Physical base address of the IP registers and length of memory mapped region.
49 - reg-names: names of the mapped memory regions listed in regs property in
60 - reg: Physical base address of the IP registers and length of memory mapped region.
61 - reg-names: names of the mapped memory regions listed in regs property in
76 - reg: Physical base address of the IP registers and length of memory mapped region.
77 - reg-names: names of the mapped memory regions listed in regs property in
89 - reg: Physical base address of the IP registers and length of memory mapped region.
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| /Documentation/admin-guide/mm/ |
| D | pagemap.rst | 12 physical frame each virtual page is mapped to. It contains one 64-bit
21 * Bit 56 page exclusively mapped (since 4.2)
38 precisely which pages are mapped (or in swap) and comparing mapped
42 determine which areas of memory are actually mapped and llseek to
46 times each page is mapped, indexed by PFN.
49 number of times a page is mapped.
122 Contiguous pages which construct THP of any size and mapped by any granularity.
166 A memory mapped page.
168 A memory mapped page that is not part of a file.
170 The page is mapped to swap space, i.e. has an associated swap entry.
[all …]
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| /Documentation/admin-guide/device-mapper/ |
| D | delay.rst | 35 # Create mapped device named "delayed" delaying read, write and flush operations for 500ms.
42 # Create mapped device delaying write and flush operations for 400ms and
51 # Create mapped device delaying reads for 50ms, writes for 100ms and flushs for 333ms
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| /Documentation/arch/loongarch/ |
| D | introduction.rst | 293 LoongArch supports direct-mapped virtual memory and page-mapped virtual memory.
295 Direct-mapped virtual memory is configured by CSR.DMWn (n=0~3), it has a simple
300 Page-mapped virtual memory has arbitrary relationship between VA and PA, which
309 ``UVRANGE`` ``0x00000000 - 0x7FFFFFFF`` Page-mapped, Cached, PLV0~3
310 ``KPRANGE0`` ``0x80000000 - 0x9FFFFFFF`` Direct-mapped, Uncached, PLV0
311 ``KPRANGE1`` ``0xA0000000 - 0xBFFFFFFF`` Direct-mapped, Cached, PLV0
312 ``KVRANGE`` ``0xC0000000 - 0xFFFFFFFF`` Page-mapped, Cached, PLV0
315 User mode (PLV3) can only access UVRANGE. For direct-mapped KPRANGE0 and
317 direct-mapped VA of 0x00001000 is 0x80001000, and the cached direct-mapped
325 ``XUVRANGE`` ``0x0000000000000000 - Page-mapped, Cached, PLV0~3
[all …]
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| /Documentation/scsi/ |
| D | g_NCR5380.rst | 16 memory mapped modes.
38 base=xx[,...] the port or base address(es) (for port or memory mapped, resp.)
55 mapped, resp.)
71 E.g. a port mapped NCR5380 board, driver to probe for IRQ::
79 E.g. a memory mapped NCR53C400 board with no IRQ::
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| /Documentation/input/ |
| D | gamepad.rst | 72 features that you need, first. How each feature is mapped is described below.
152 If analog-sticks provide digital buttons, they are mapped accordingly as
174 Menu buttons are always digital and are mapped according to their location
179 Mapped as BTN_START
183 Left button mapped as BTN_SELECT, right button mapped as BTN_START
186 and meaning. Such buttons are mapped as BTN_MODE. Examples are the Nintendo
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| /Documentation/devicetree/bindings/clock/ |
| D | fixed-mmio-clock.yaml | 7 title: Simple memory mapped IO fixed-rate clock sources
11 be read from a single 32-bit memory mapped I/O register.
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| /Documentation/devicetree/bindings/net/ |
| D | mdio-mux-mmioreg.yaml | 7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
15 node must be a child of the memory-mapped device. The driver currently only
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| /Documentation/driver-api/ |
| D | io_ordering.rst | 2 Ordering I/O writes to memory-mapped addresses
5 On some platforms, so-called memory-mapped I/O is weakly ordered. On such
7 memory-mapped addresses on their device arrive in the order intended. This is
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| /Documentation/devicetree/bindings/arm/ |
| D | vexpress-scc.txt | 8 In some cases its registers are also mapped in normal address space
23 - reg: when the SCC is memory mapped, physical address and size of the
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| /Documentation/firmware-guide/acpi/ |
| D | lpit.rst | 13 (Function fixed hardware) or a memory mapped interface.
19 - Platform Controller Hub (PCH) SLP_S0 (Read via memory mapped interface)
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| /Documentation/devicetree/bindings/net/pcs/ |
| D | snps,dw-xpcs.yaml | 22 by means of the APB3/MCI interfaces. In the later case the XPCS can be mapped
52 registers are contiguously mapped within the address space
57 so the corresponding subset would be mapped to the lowest 255 CSRs.
65 The way the CSRs are mapped to the memory is platform depended. Since
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| /Documentation/ABI/testing/ |
| D | sysfs-class-intel_pmt | 18 may be opened and mapped or read to access the telemetry space
29 may be mapped or read to obtain the data.
64 file. This file can be opened and mapped or read to access the
75 may be mapped or read to obtain the data.
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| /Documentation/devicetree/bindings/power/reset/ |
| D | syscon-reboot-mode.yaml | 14 and stores it in a SYSCON mapped register. Then the bootloader
16 value stored. The SYSCON mapped register is retrieved from the
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer_mmio.yaml | 7 title: ARM memory mapped architected timer
14 ARM cores may have a memory mapped architected timer, which provides up to 8
17 The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
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