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/Documentation/ABI/testing/
Dsysfs-bus-soundwire-master1 What: /sys/bus/soundwire/devices/sdw-master-<N>/revision
2 /sys/bus/soundwire/devices/sdw-master-<N>/clk_stop_modes
3 /sys/bus/soundwire/devices/sdw-master-<N>/clk_freq
4 /sys/bus/soundwire/devices/sdw-master-<N>/clk_gears
5 /sys/bus/soundwire/devices/sdw-master-<N>/default_col
6 /sys/bus/soundwire/devices/sdw-master-<N>/default_frame_rate
7 /sys/bus/soundwire/devices/sdw-master-<N>/default_row
8 /sys/bus/soundwire/devices/sdw-master-<N>/dynamic_shape
9 /sys/bus/soundwire/devices/sdw-master-<N>/err_threshold
10 /sys/bus/soundwire/devices/sdw-master-<N>/max_clk_freq
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Dsysfs-bus-fsi1 What: /sys/bus/platform/devices/../fsi-master/fsi0/rescan
6 Initiates a FSI master scan for all connected slave devices
9 What: /sys/bus/platform/devices/../fsi-master/fsi0/break
14 Sends an FSI BREAK command on a master's communication
17 from the master.
19 What: /sys/bus/platform/devices/../fsi-master/fsi0/slave@00:00/term
24 Sends an FSI terminate command from the master to its
29 ongoing operation in case of an expired 'Master Time Out'
32 What: /sys/bus/platform/devices/../fsi-master/fsi0/slave@00:00/raw
Dsysfs-class-stm6 Shows first and last available to software master numbers on
14 Shows the number of channels per master on this STM device.
21 Reads as 0 if master numbers in the STP stream produced by
22 this stm device will match the master numbers assigned by
/Documentation/devicetree/bindings/iommu/
Diommu.txt2 master(s).
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
46 - #iommu-cells = <0>: Single master IOMMU devices are not configurable and
48 This may also apply to multiple master IOMMU devices that do not allow the
50 be multi-master yet only expose a single master in a given configuration.
52 - #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
53 in order to enable translation for a given master. In such cases the single
54 address cell corresponds to the master device's ID. In some cases more than
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/Documentation/scsi/
Dadvansys.rst21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
29 - ABP915 - Bus-Master PCI (16 CDB)
30 - ABP920 - Bus-Master PCI (16 CDB)
31 - ABP3922 - Bus-Master PCI (16 CDB)
32 - ABP3925 - Bus-Master PCI (16 CDB)
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/Documentation/devicetree/bindings/soc/qcom/
Dqcom,rpm-master-stats.yaml4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpm-master-stats.yaml#
7 title: Qualcomm Technologies, Inc. (QTI) RPM Master Stats
17 and total system-wide power collapse) are first made at Master-level, and
20 The Master Stats provide a few useful bits that can be used to assess whether
31 const: qcom,rpm-master-stats
35 description: Phandle to an RPM MSG RAM slice containing the master stats
41 qcom,master-names:
44 The name of the RPM Master which owns the MSG RAM slice where this
45 instance of Master Stats resides
52 - qcom,master-names
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/Documentation/devicetree/bindings/fsi/
Dfsi.txt8 that is an I2C master - the I2C bus can be described by the device tree under
11 FSI masters may require their own DT nodes (to describe the master HW itself);
12 that requirement is defined by the master's implementation, and is described by
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
46 FSI master nodes declare themselves as such with the "fsi-master" compatible
50 compatible = "fsi-master-gpio", "fsi-master";
52 Since the master nodes describe the top-level of the FSI topology, they also
59 An optional boolean property can be added to indicate that a particular master
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Daspeed,ast2600-fsi-master.yaml4 $id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml#
7 title: Aspeed FSI master
19 - aspeed,ast2600-fsi-master
20 - aspeed,ast2700-fsi-master
48 - aspeed,ast2600-fsi-master
83 fsi-master@1e79b000 {
84 compatible = "aspeed,ast2600-fsi-master";
108 fsi-master@21800000 {
109 compatible = "aspeed,ast2700-fsi-master";
Dibm,i2cr-fsi-master.yaml4 $id: http://devicetree.org/schemas/fsi/ibm,i2cr-fsi-master.yaml#
7 title: IBM I2C Responder virtual FSI master
15 writes or SCOM operations, thereby acting as an FSI master.
20 - ibm,i2cr-fsi-master
41 compatible = "ibm,i2cr-fsi-master";
Dfsi-master-ast-cf.txt1 Device-tree bindings for ColdFire offloaded gpio-based FSI master driver
6 "aspeed,ast2400-cf-fsi-master" for an AST2400 based system
8 "aspeed,ast2500-cf-fsi-master" for an AST2500 based system
24 fsi-master {
25 compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master";
Dfsi-master-gpio.txt1 Device-tree bindings for gpio-based FSI master driver
5 - compatible = "fsi-master-gpio";
21 fsi-master {
22 compatible = "fsi-master-gpio", "fsi-master";
/Documentation/driver-api/soundwire/
Dsummary.rst23 (4) Device status monitoring, including interrupt-style alerts to the Master.
35 Below figure shows an example of connectivity between a SoundWire Master and
40 | Master |-------+-------------------------------| Slave |
58 The MIPI SoundWire specification uses the term 'device' to refer to a Master
70 Master. Multiple instances of Bus may be present in a system.
78 directly by the Bus (and transmitted through the Master driver/interface).
83 Programming interfaces (SoundWire Master interface Driver)
86 SoundWire Bus supports programming interfaces for the SoundWire Master
90 Each of the SoundWire Master interfaces needs to be registered to the Bus.
91 Bus implements API to read standard Master MIPI properties and also provides
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/Documentation/devicetree/bindings/spi/
Dicpdas-lp8841-spi-rtc.txt4 memory register, which acts as an SPI master device.
7 Master output is set on low clock and sensed by the RTC on the rising
8 edge. Master input is set by the RTC on the trailing edge and is sensed
9 by the master on low clock.
28 - spi-3wire: The master itself has only 3 wire. It cannor work in
31 - spi-cs-high: DS-1302 has active high chip select line. The master
35 transfers. The master only support this type of bit ordering.
/Documentation/w1/
Dw1-netlink.rst10 1. Events. They are generated each time a new master or slave device
30 master add/remove events
32 userspace command for bus master
42 __u32 id; - master's id
47 [struct w1_netlink_cmd] - command for given master or slave device.
72 or master's id, which is assigned to bus master device
88 which will contain list of all registered master ids in the following
97 Each message is at most 4k in size, so if number of master devices
106 id is equal to the bus master id to use for searching]
133 id is equal to the bus master id to use for searching]
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/Documentation/networking/dsa/
Dconfiguration.rst124 ip link set dev lan1 master br0
125 ip link set dev lan2 master br0
126 ip link set dev lan3 master br0
153 ip link set dev lan1 master br0
154 ip link set dev lan2 master br0
200 ip link set dev lan1 master br0
201 ip link set dev lan2 master br0
202 ip link set dev lan3 master br0
241 ip link set dev lan1 master br0
242 ip link set dev lan2 master br0
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Db53.rst89 ip link set dev wan master br0
90 ip link set dev lan1 master br0
91 ip link set dev lan2 master br0
132 ip link set dev wan master br0
133 ip link set dev lan1 master br0
134 ip link set dev lan2 master br0
135 ip link set eth0.1 master br0
169 ip link set dev wan master br0
170 ip link set eth0.1 master br0
171 ip link set dev lan1 master br0
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/Documentation/devicetree/bindings/sound/
Dmikroe,mikroe-proto.txt10 - bitclock-master: Indicates dai-link bit clock master; for details see simple-card.txt (1).
11 - frame-master: Indicates dai-link frame master; for details see simple-card.txt (1).
13 (1) : There must be the same master for both bit and frame clocks.
Dfsl,ssi.yaml65 - description: clock for SSI master mode
132 enum: [ ac97-slave, ac97-master, i2s-slave, i2s-master,
133 lj-slave, lj-master, rj-slave, rj-master ]
136 "ac97-master" - AC97 mode, SSI is clock master
138 "i2s-master" - I2S mode, SSI is clock master
140 "lj-master" - Left justified mode, SSI is clock master
142 "rj-master" - Right justified mode, SSI is clock master
/Documentation/devicetree/bindings/ata/
Dcortina,gemini-sata-bridge.yaml56 Mode 0: ata0 master <-> sata0
57 ata1 master <-> sata1
59 Mode 1: ata0 master <-> sata0
60 ata1 master <-> sata1
62 Mode 2: ata1 master <-> sata1
64 ata0 master and slave interfaces brought out on IDE pads
65 Mode 3: ata0 master <-> sata0
67 ata1 master and slave interfaces brought out on IDE pads
73 and whether master, slave or both interfaces get brought out.
/Documentation/i2c/
Dgpio-fault-injection.rst5 The GPIO based I2C bus master driver can be configured to provide fault
7 which is driven by the I2C bus master driver under test. The GPIO fault
9 master driver should handle gracefully.
26 because the bus master under test will not be able to clock. It should detect
36 master under test should detect this condition and trigger a bus recovery (see
52 in a bus master driver, make sure you checked your hardware setup for such
63 above, the bus master under test should detect this condition and try a bus
89 Here, we want to simulate the condition where the master under test loses the
90 bus arbitration against another master in a multi-master setup.
99 Arbitration lost is achieved by waiting for SCL going down by the master under
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/Documentation/networking/device_drivers/ethernet/ti/
Dcpsw_switchdev.rst69 ip link set dev sw0p1 master br0
70 ip link set dev sw0p2 master br0
78 ip link set dev sw0p1 master br0
79 ip link set dev sw0p2 master br0
112 ip link set dev sw0p1 master br0
113 ip link set dev sw0p2 master br0
143 bridge vlan add dev sw0p1 vid 100 pvid untagged master
144 bridge vlan add dev sw0p2 vid 100 pvid untagged master
149 bridge vlan add dev sw0p1 vid 100 master
150 bridge vlan add dev sw0p2 vid 100 master
[all …]
Dam65_nuss_cpsw_switchdev.rst62 ip link set dev sw0p1 master br0
63 ip link set dev sw0p2 master br0
93 bridge vlan add dev sw0p1 vid 100 pvid untagged master
94 bridge vlan add dev sw0p2 vid 100 pvid untagged master
99 bridge vlan add dev sw0p1 vid 100 master
100 bridge vlan add dev sw0p2 vid 100 master
110 bridge fdb add aa:bb:cc:dd:ee:ff dev sw0p1 master vlan 100
111 bridge fdb add aa:bb:cc:dd:ee:fe dev sw0p2 master <---- Add on all VLANs
135 bridge vlan add dev sw0p1 vid 100 pvid untagged master
136 bridge vlan add dev sw0p2 vid 100 master
/Documentation/sound/soc/
Dclocking.rst9 Master Clock
12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
13 or SYSCLK). This audio master clock can be derived from a number of sources
17 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
19 power). Other master clocks are fixed at a set frequency (i.e. crystals).
42 It is also desirable to use the codec (if possible) to drive (or master) the
/Documentation/driver-api/nvdimm/
Dsecurity.rst33 master_update <keyid> <new_keyid> - enable or update master passphrase.
55 encrypted-keys of enc32 format. TPM usage with a master trusted key is
118 10. Master Update
120 The command format for doing a master update is:
123 The operating mechanism for master update is identical to update except the
124 master passphrase key is passed to the kernel. The master passphrase key
129 11. Master Erase
131 The command format for doing a master erase is:
134 This command has the same operating mechanism as erase except the master
135 passphrase key is passed to the kernel. The master passphrase key is just
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/Documentation/trace/
Dstm.rst10 which is assigned a unique pair of master and channel. While some of
14 master/channel combination from this pool.
17 sources can only be identified by master/channel combination, so in
20 master/channel pairs to the trace sources that it understands.
23 master 7 channel 15, while arbitrary user applications can use masters
47 which means that the master allocation pool for this rule consists of
50 with "user" identification string will be allocated a master and
78 contiguous range of master/channels from the beginning of the device's
79 master/channel range. The new requirement for a policy node to exist
109 Each stm_source device will need to assume a master and a range of
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