Searched full:masters (Results 1 – 25 of 62) sorted by relevance
123
| /Documentation/devicetree/bindings/dma/ |
| D | nxp,lpc3220-dmamux.yaml | 23 dma-masters:
30 First two cells same as for device pointed in dma-masters.
36 - dma-masters
45 dma-masters = <&dma>;
|
| D | dma-router.yaml | 25 dma-masters:
39 - dma-masters
|
| D | snps,dw-axi-dmac.yaml | 66 snps,dma-masters:
68 Number of AXI masters supported by the hardware.
110 - snps,dma-masters
150 snps,dma-masters = <2>;
|
| D | renesas,rzn1-dmamux.yaml | 30 dma-masters:
49 dma-masters = <&dma0 &dma1>;
|
| D | lpc1850-dmamux.txt | 12 - dma-masters: phandle pointing to the DMA controller
41 dma-masters = <&dmac>;
|
| D | snps,dma-spear1340.yaml | 62 dma-masters:
65 Number of DMA masters supported by the controller. In case if
175 dma-masters = <4>;
|
| D | ti-dma-crossbar.txt | 10 - dma-masters: phandle pointing to the DMA controller
55 dma-masters = <&sdma>;
|
| /Documentation/devicetree/bindings/iommu/ |
| D | iommu.txt | 49 association of masters to be configured. Note that an IOMMU can by design
56 - #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
70 Devices that access memory through an IOMMU are called masters. A device can
91 - pasid-num-bits: Some masters support multiple address spaces for DMA, by
105 Firmware has to opt-in stalling, because most buses and masters don't
108 won't work in systems and masters that haven't been designed for
146 * Masters are statically associated with this IOMMU and share
148 * have sufficient information to distinguish between masters.
151 * all masters at any given point in time.
|
| /Documentation/trace/ |
| D | stm.rst | 11 these masters and channels are statically allocated to certain
23 master 7 channel 15, while arbitrary user applications can use masters
28 identifiers to ranges of masters and channels. If these rules (policy)
33 have a name (string identifier) and a range of masters and channels
41 channels masters
42 $ cat /config/stp-policy/dummy_stm.my-policy/user/masters
48 masters 48 through 63 and channel allocation pool has channels 0
|
| D | intel_th.rst | 37 GTH allows directing different STP masters into different output ports
38 via its "masters" attribute group. More detailed GTH interface
79 $ echo 0 > /sys/bus/intel_th/devices/0-gth/masters/33
|
| /Documentation/ABI/testing/ |
| D | sysfs-class-stm | 1 What: /sys/class/stm/<stm>/masters
24 assigned masters.
|
| D | configfs-stp-policy | 34 What: /config/stp-policy/<device>.<policy>/<node>/masters
38 Range of masters from which to allocate for users of this node.
|
| D | sysfs-bus-intel_th-devices-gth | 1 What: /sys/bus/intel_th/devices/<intel_th_id>-gth/masters/*
5 Description: (RW) Configure output ports for STP masters. Writing -1
|
| D | sysfs-platform-i2c-demux-pinctrl | 6 Reading the file will give you a list of masters which can be
|
| /Documentation/devicetree/bindings/arm/ |
| D | cci-control-port.yaml | 7 title: CCI Interconnect Bus Masters
13 Masters in the device tree connected to a CCI port (inclusive of CPUs
|
| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-dmamux.yaml | 38 - dma-masters
53 dma-masters = <&dma1>, <&dma2>;
|
| /Documentation/devicetree/bindings/fsi/ |
| D | fsi.txt | 11 FSI masters may require their own DT nodes (to describe the master HW itself);
15 Under the masters' nodes, we can describe the bus topology using nodes to
43 FSI masters
62 masters that may be present on the bus.
|
| D | fsi-master-gpio.txt | 13 functions (eg, external FSI masters)
|
| /Documentation/devicetree/bindings/bus/ |
| D | brcm,gisb-arb.yaml | 41 32-bits wide bitmask used to specify which GISB masters are valid at the
47 String list of the literal name of the GISB masters. Should match the
|
| D | ti,da850-mstpri.txt | 5 peripherals classified as masters.
|
| /Documentation/w1/ |
| D | index.rst | 13 masters/index
|
| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-gate.yaml | 16 there are no competing masters to consider for gates and therefore there is
|
| D | i2c-arb-gpio-challenge.yaml | 24 * Having two masters on a bus in general makes it relatively hard to debug
29 All masters on the bus have a 'bus claim' line which is an output that the
|
| /Documentation/devicetree/bindings/soc/renesas/ |
| D | renesas,r9a09g057-sys.yaml | 16 - Extend access by specific masters to address beyond 4GB space
|
| /Documentation/devicetree/bindings/soc/mediatek/ |
| D | devapc.yaml | 12 protection to prevent slaves from being accessed by unexpected masters.
|
123