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/Documentation/admin-guide/pm/
Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Intel(R) Speed Select Technology User Guide
7 The Intel(R) Speed Select Technology (Intel(R) SST) provides a powerful new
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
21 and configure these features is by using the Intel Speed Select utility.
23 This document explains how to use the Intel Speed Select tool to enumerate and
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
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/Documentation/devicetree/bindings/net/bluetooth/
Dmarvell,88w8897.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Rob Herring <robh@kernel.org>
19 - mrvl,88w8897
20 - mrvl,88w8997
22 max-speed: true
25 - compatible
28 - $ref: /schemas/serial/serial-peripheral-props.yaml#
29 - if:
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/Documentation/devicetree/bindings/usb/
Dusb251xb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip USB 2.0 Hi-Speed Hub Controller
10 - Richard Leitner <richard.leitner@skidata.com>
15 - microchip,usb2422
16 - microchip,usb2512b
17 - microchip,usb2512bi
18 - microchip,usb2513b
19 - microchip,usb2513bi
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/Documentation/hwmon/
Dadm1026.rst16 - Philip Pokorny <ppokorny@penguincomputing.com> for Penguin Computing
17 - Justin Thiessen <jthiessen@penguincomputing.com>
20 -----------------
22 * gpio_input: int array (min = 1, max = 17)
23 List of GPIO pins (0-16) to program as inputs
25 * gpio_output: int array (min = 1, max = 17)
26 List of GPIO pins (0-16) to program as outputs
28 * gpio_inverted: int array (min = 1, max = 17)
29 List of GPIO pins (0-16) to program as inverted
31 * gpio_normal: int array (min = 1, max = 17)
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Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
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Dbel-pfe.rst1 Kernel driver bel-pfe
10 Addresses scanned: -
12 … Datasheet: https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-pfe1100-12-054xa.pdf
18 Addresses scanned: -
20 Datasheet: https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-pfe3000-series.pdf
26 -----------
33 1100 Watt AC to DC power-factor-corrected (PFC) power supply.
38 3000 Watt AC/DC power-factor-corrected (PFC) and DC-DC power supply.
46 -----------
48 This driver does not auto-detect devices. You will have to instantiate the
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Dpwm-fan.rst1 Kernel driver pwm-fan
12 -----------
19 The fan rotation speed returned via the optional 'fan1_input' is extrapolated
25 fan1_input ro fan tachometer speed in RPM
27 0 -> disable pwm and regulator
28 1 -> enable pwm; if pwm==0, disable pwm, keep regulator enabled
29 2 -> enable pwm; if pwm==0, keep pwm and regulator enabled
30 3 -> enable pwm; if pwm==0, disable pwm and regulator
31 pwm1 rw relative speed (0-255), 255=max. speed.
/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr2-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
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Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
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/Documentation/devicetree/bindings/pci/
Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
20 - const: ti,am64-pcie-ep
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Drcar-gen4-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Renesas Electronics Corp.
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Gen4 PCIe Endpoint
11 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
14 - $ref: snps,dw-pcie-ep.yaml#
19 - enum:
20 - renesas,r8a779f0-pcie-ep # R-Car S4-8
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Dti,am65-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: pci-ep.yaml#
19 - ti,am654-pcie-ep
24 reg-names:
26 - const: app
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/Documentation/devicetree/bindings/net/ieee802154/
Dadf7242.txt4 - compatible: should be "adi,adf7242", "adi,adf7241"
5 - spi-max-frequency: maximal bus speed (12.5 MHz)
6 - reg: the chipselect index
7 - interrupts: the interrupt generated by the device via pin IRQ1.
14 spi-max-frequency = <10000000>;
17 interrupt-parent = <&gpio3>;
Dmrf24j40.txt4 - compatible: should be "microchip,mrf24j40", "microchip,mrf24j40ma",
7 - spi-max-frequency: maximal bus speed, should be set something under or equal
9 - reg: the chipselect index
10 - interrupts: the interrupt generated by the device.
16 spi-max-frequency = <8500000>;
19 interrupt-parent = <&gpio3>;
Dmcr20a.txt4 - compatible: should be "nxp,mcr20a"
5 - spi-max-frequency: maximal bus speed, should be set to a frequency
7 - reg: the chipselect index
8 - interrupts: the interrupt generated by the device. Non high-level
12 - rst_b-gpio: GPIO spec for the RST_B pin
18 spi-max-frequency = <9000000>;
21 interrupt-parent = <&gpio>;
22 rst_b-gpio = <&gpio 27 1>
Dca8210.txt4 - compatible: Should be "cascoda,ca8210"
5 - reg: Controlling chip select
6 - spi-max-frequency: Maximum clock speed, should be *less than*
8 - spi-cpol: Requires inverted clock polarity
9 - reset-gpio: GPIO attached to reset
10 - irq-gpio: GPIO attached to IRQ
12 - extclock-enable: Include for the ca8210 to route its 16MHz clock
14 - extclock-freq: Frequency in Hz of the external clock
15 - extclock-gpio: GPIO of the ca8210 to output the clock on
21 spi-max-frequency = <3000000>;
[all …]
Dat86rf230.txt4 - compatible: should be "atmel,at86rf230", "atmel,at86rf231",
6 - spi-max-frequency: maximal bus speed, should be set to 7500000 depends
8 - reg: the chipselect index
9 - interrupts: the interrupt generated by the device. Non high-level
13 - reset-gpio: GPIO spec for the rstn pin
14 - sleep-gpio: GPIO spec for the slp_tr pin
15 - xtal-trim: u8 value for fine tuning the internal capacitance
22 spi-max-frequency = <7500000>;
25 interrupt-parent = <&gpio3>;
26 xtal-trim = /bits/ 8 <0x06>;
/Documentation/devicetree/bindings/hwmon/
Dgpio-fan.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/hwmon/gpio-fan.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 const: gpio-fan
19 ordered MSB-->LSB.
23 alarm-gpios:
26 gpio-fan,speed-map:
27 $ref: /schemas/types.yaml#/definitions/uint32-matrix
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/Documentation/devicetree/bindings/misc/
Dlwn-bk4.txt10 - compatible : Should be "lwn,bk4"
14 - reg : Should be address of the device chip select within
17 - spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
24 spi-max-frequency = <30000000>;
/Documentation/devicetree/bindings/net/can/
Dcan-transceiver.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/can/can-transceiver.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Rob Herring <robh@kernel.org>
15 max-bitrate:
17 description: a positive non 0 value that determines the max speed that CAN/CAN-FD can run.
/Documentation/devicetree/bindings/media/spi/
Dsony-cxd2880.txt1 Sony CXD2880 DVB-T2/T tuner + demodulator driver SPI adapter
4 - compatible: Should be "sony,cxd2880".
5 - reg: SPI chip select number for the device.
6 - spi-max-frequency: Maximum bus speed, should be set to <55000000> (55MHz).
9 - vcc-supply: Optional phandle to the vcc regulator to power the adapter,
17 spi-max-frequency = <55000000>; /* 55MHz */
/Documentation/sound/cards/
Dhdspm.rst2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
29 * Single Speed -- 1..64 channels
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
41 transmission/receive-mode , only 28 are transmitted/received
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/Documentation/devicetree/bindings/hsi/
Dclient-devices.txt7 - hsi-channel-ids: A list of channel ids
9 - hsi-rx-mode: Receiver Bit transmission mode ("stream" or "frame")
10 - hsi-tx-mode: Transmitter Bit transmission mode ("stream" or "frame")
11 - hsi-mode: May be used instead hsi-rx-mode and hsi-tx-mode if
14 - hsi-speed-kbps: Max bit transmission speed in kbit/s
15 - hsi-flow: RX flow type ("synchronized" or "pipeline")
16 - hsi-arb-mode: Arbitration mode for TX frame ("round-robin", "priority")
20 - hsi-channel-names: A list with one name per channel specified in the
21 hsi-channel-ids property
26 hsi-controller {
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/Documentation/devicetree/bindings/sound/
Dst,sta32x.txt7 - compatible: "st,sta32x"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - Vdda-supply: regulator spec, providing 3.3V
17 - Vdd3-supply: regulator spec, providing 3.3V
18 - Vcc-supply: regulator spec, providing 5V - 26V
22 - clocks, clock-names: Clock specifier for XTI input clock.
24 and disabled when it is removed. The 'clock-names' must be set to 'xti'.
26 - st,output-conf: number, Selects the output configuration:
[all …]
Dst,sta350.txt7 - compatible: "st,sta350"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - vdd-dig-supply: regulator spec, providing 3.3V
17 - vdd-pll-supply: regulator spec, providing 3.3V
18 - vcc-supply: regulator spec, providing 5V - 26V
22 - st,output-conf: number, Selects the output configuration:
23 0: 2-channel (full-bridge) power, 2-channel data-out
24 1: 2 (half-bridge). 1 (full-bridge) on-board power
[all …]

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