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/Documentation/devicetree/bindings/net/dsa/
Drealtek.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: dsa.yaml#/$defs/ethernet-ports
13 - Linus Walleij <linus.walleij@linaro.org>
18 MDIO or SPI.
20 The SMI "Simple Management Interface" is a two-wire protocol using
21 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
22 not use the MDIO protocol. This binding defines how to specify the
23 SMI-based Realtek devices. The realtek-smi driver is a platform driver
[all …]
Dlan9303.txt2 -------------------------------------------------
6 - compatible: should be
7 - "smsc,lan9303-i2c" for I2C managed mode
9 - "smsc,lan9303-mdio" for mdio managed mode
13 - reset-gpios: GPIO to be used to reset the whole device
14 - reset-duration: reset duration in milliseconds, defaults to 200 ms
23 auto-detected and mapped accordingly.
31 fixed-link { /* RMII fixed link to LAN9303 */
33 full-duplex;
38 compatible = "smsc,lan9303-i2c";
[all …]
Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
19 the MDIO master is used for communication. Mixed external and internal
20 mdio-bus configurations are not supported by the hardware.
27 - enum:
[all …]
Dmarvell,mv88e6xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
22 - enum:
23 - marvell,mv88e6085
24 - marvell,mv88e6190
25 - marvell,mv88e6250
43 - items:
44 - const: marvell,turris-mox-mv88e6085
[all …]
Dmarvell,mv88e6060.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
15 MDIO address of the switch to be 0x10 or 0x00, and on the MDIO bus
17 independent devices on address 0x00-0x04 or 0x10-0x14, so in difference
19 MDIO bus for the PHY devices.
31 reset-gpios:
37 - $ref: dsa.yaml#/$defs/ethernet-ports
40 - compatible
[all …]
Drenesas,rzn1-a5psw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clément Léger <clement.leger@bootlin.com>
17 - $ref: dsa.yaml#/$defs/ethernet-ports
22 - enum:
23 - renesas,r9a06g032-a5psw
24 - const: renesas,rzn1-a5psw
31 - description: Device Level Ring (DLR) interrupt
[all …]
Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
22 - microchip,lan9374
[all …]
Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
Dmicrochip,ksz.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
11 - Woojung Huh <Woojung.Huh@microchip.com>
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
21 - microchip,ksz8765
22 - microchip,ksz8794
23 - microchip,ksz8795
24 - microchip,ksz8863
[all …]
/Documentation/devicetree/bindings/net/
Dmdio-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO on GPIOs
10 - Andrew Lunn <andrew@lunn.ch>
11 - Heiner Kallweit <hkallweit1@gmail.com>
12 - Russell King <linux@armlinux.org.uk>
15 - $ref: mdio.yaml#
20 - virtual,mdio-gpio
[all …]
Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO Bus Common Properties
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
15 These are generic properties that can apply to any MDIO bus. Any
16 MDIO bus must have a list of child nodes, one per device on the
[all …]
Dmdio-mux-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. One or more GPIO
17 - $ref: /schemas/net/mdio-mux.yaml#
21 const: mdio-mux-gpio
23 gpios:
[all …]
Dnixge.txt4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
5 older device trees with DMA engines co-located in the address map,
7 - reg: Address and length of the register set for the device. It contains the
8 information of registers in the same order as described by reg-names.
9 - reg-names: Should contain the reg names
11 "ctrl": MDIO and PHY control and status region
12 - interrupts: Should contain tx and rx interrupt
13 - interrupt-names: Should be "rx" and "tx"
14 - phy-mode: See ethernet.txt file in the same directory.
15 - nvmem-cells: Phandle of nvmem cell containing the MAC address
[all …]
Dfsl,fec.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
[all …]
Drenesas,ethertsn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet TSN End-station
10 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - renesas,r8a779g0-ethertsn # R-Car V4H
24 - const: renesas,rcar-gen4-ethertsn
[all …]
Dapm-xgene-enet.txt1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
[all …]
Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
Dsff,sfp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
11 - Russell King <linux@armlinux.org.uk>
16 - sff,sfp # for SFP modules
17 - sff,sff # for soldered down SFF modules
19 i2c-bus:
24 maximum-power-milliwatt:
29 allowable by a module in the slot, in milli-Watts. Presently, modules can
[all …]
Drenesas,ether.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
18 - items:
19 - enum:
20 - renesas,gether-r8a7740 # device is a part of R8A7740 SoC
21 - renesas,gether-r8a77980 # device is a part of R8A77980 SoC
22 - renesas,ether-r7s72100 # device is a part of R7S72100 SoC
[all …]
Drenesas,etheravb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
[all …]
Dmediatek,net.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
[all …]
Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
[all …]
Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
[all …]
/Documentation/devicetree/bindings/clock/
Dqcom,qca8k-nsscc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Luo Jie <quic_luoj@quicinc.com>
18 include/dt-bindings/clock/qcom,qca8k-nsscc.h
19 include/dt-bindings/reset/qcom,qca8k-nsscc.h
24 - const: qcom,qca8084-nsscc
25 - items:
[all …]
/Documentation/devicetree/bindings/firmware/
Dintel,ixp4xx-network-processing-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
16 and crypto tasks. It also manages the MDIO bus to the ethernet PHYs
24 - items:
25 - const: intel,ixp4xx-network-processing-engine
29 - description: NPE0 (NPE-A) register range
30 - description: NPE1 (NPE-B) register range
[all …]

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