| /Documentation/devicetree/bindings/clock/ |
| D | mediatek,syscon.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,syscon.yaml#
7 title: MediaTek Clock controller syscon's
14 The MediaTek clock controller syscon's provide various clocks to the system.
21 - mediatek,mt2701-bdpsys
22 - mediatek,mt2701-imgsys
23 - mediatek,mt2701-vdecsys
24 - mediatek,mt2712-bdpsys
25 - mediatek,mt2712-imgsys
26 - mediatek,mt2712-jpgdecsys
27 - mediatek,mt2712-mcucfg
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| D | mediatek,mt8188-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8188
10 - Garmin Chang <garmin.chang@mediatek.com>
13 The clock architecture in MediaTek like below
25 - mediatek,mt8188-adsp-audio26m
26 - mediatek,mt8188-camsys
27 - mediatek,mt8188-camsys-rawa
28 - mediatek,mt8188-camsys-rawb
29 - mediatek,mt8188-camsys-yuva
30 - mediatek,mt8188-camsys-yuvb
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| D | mediatek,infracfg.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml#
7 title: MediaTek Infrastructure System Configuration Controller
13 The Mediatek infracfg controller provides various clocks and reset outputs
23 - mediatek,mt2701-infracfg
24 - mediatek,mt2712-infracfg
25 - mediatek,mt6765-infracfg
26 - mediatek,mt6795-infracfg
27 - mediatek,mt6779-infracfg_ao
28 - mediatek,mt6797-infracfg
29 - mediatek,mt7622-infracfg
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| D | mediatek,mt8195-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8195
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The clock architecture in Mediatek like below
27 - mediatek,mt8195-scp_adsp
28 - mediatek,mt8195-imp_iic_wrap_s
29 - mediatek,mt8195-imp_iic_wrap_w
30 - mediatek,mt8195-mfgcfg
31 - mediatek,mt8195-wpesys
32 - mediatek,mt8195-wpesys_vpp0
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| D | mediatek,topckgen.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#
7 title: MediaTek Top Clock Generator Controller
14 The Mediatek topckgen controller provides various clocks to the system.
21 - mediatek,mt6797-topckgen
22 - mediatek,mt7622-topckgen
23 - mediatek,mt8135-topckgen
24 - mediatek,mt8173-topckgen
25 - mediatek,mt8516-topckgen
27 - const: mediatek,mt7623-topckgen
28 - const: mediatek,mt2701-topckgen
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| D | mediatek,apmixedsys.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#
7 title: MediaTek AP Mixedsys Controller
14 The Mediatek apmixedsys controller provides PLLs to the system.
21 - mediatek,mt6797-apmixedsys
22 - mediatek,mt7622-apmixedsys
23 - mediatek,mt7981-apmixedsys
24 - mediatek,mt7986-apmixedsys
25 - mediatek,mt7988-apmixedsys
26 - mediatek,mt8135-apmixedsys
27 - mediatek,mt8173-apmixedsys
[all …]
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| D | mediatek,mt8192-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8192
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The Mediatek functional clock controller provides various clocks on MT8192.
19 - mediatek,mt8192-scp_adsp
20 - mediatek,mt8192-imp_iic_wrap_c
21 - mediatek,mt8192-imp_iic_wrap_e
22 - mediatek,mt8192-imp_iic_wrap_s
23 - mediatek,mt8192-imp_iic_wrap_ws
24 - mediatek,mt8192-imp_iic_wrap_w
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| D | mediatek,pericfg.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,pericfg.yaml#
7 title: MediaTek Peripheral Configuration Controller
13 The Mediatek pericfg controller provides various clocks and reset outputs
21 - mediatek,mt2701-pericfg
22 - mediatek,mt2712-pericfg
23 - mediatek,mt6765-pericfg
24 - mediatek,mt6795-pericfg
25 - mediatek,mt7622-pericfg
26 - mediatek,mt7629-pericfg
27 - mediatek,mt8135-pericfg
[all …]
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| D | mediatek,mt8186-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8186-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8186
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The clock architecture in MediaTek like below
26 - mediatek,mt8186-imp_iic_wrap
27 - mediatek,mt8186-mfgsys
28 - mediatek,mt8186-wpesys
29 - mediatek,mt8186-imgsys1
30 - mediatek,mt8186-imgsys2
31 - mediatek,mt8186-vdecsys
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| /Documentation/devicetree/bindings/arm/ |
| D | mediatek.yaml | 4 $id: http://devicetree.org/schemas/arm/mediatek.yaml#
7 title: MediaTek SoC based Platforms
10 - Sean Wang <sean.wang@mediatek.com>
13 Boards with a MediaTek SoC shall have the following properties.
23 - mediatek,mt2701-evb
24 - const: mediatek,mt2701
28 - mediatek,mt2712-evb
29 - const: mediatek,mt2712
32 - mediatek,mt6580-evbp1
33 - const: mediatek,mt6580
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | mediatek,mt6577-sysirq.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mediatek,mt6577-sysirq.yaml#
7 title: MediaTek sysirq
10 MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
19 - const: mediatek,mt6577-sysirq
22 - mediatek,mt2701-sysirq
23 - mediatek,mt2712-sysirq
24 - mediatek,mt6580-sysirq
25 - mediatek,mt6582-sysirq
26 - mediatek,mt6589-sysirq
27 - mediatek,mt6592-sysirq
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| /Documentation/devicetree/bindings/mfd/ |
| D | mt6397.txt | 1 MediaTek MT6397/MT6323 Multifunction Device Driver
16 ../soc/mediatek/mediatek,pwrap.yaml
22 "mediatek,mt6323" for PMIC MT6323
23 "mediatek,mt6331" for PMIC MT6331 and MT6332
24 "mediatek,mt6357" for PMIC MT6357
25 "mediatek,mt6358" for PMIC MT6358
26 "mediatek,mt6359" for PMIC MT6359
27 "mediatek,mt6366", "mediatek,mt6358" for PMIC MT6366
28 "mediatek,mt6397" for PMIC MT6397
34 - compatible: "mediatek,mt6323-rtc"
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| /Documentation/devicetree/bindings/serial/ |
| D | mediatek,uart.yaml | 4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
26 - mediatek,mt2701-uart
27 - mediatek,mt2712-uart
28 - mediatek,mt6580-uart
29 - mediatek,mt6582-uart
30 - mediatek,mt6589-uart
31 - mediatek,mt6755-uart
[all …]
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| /Documentation/devicetree/bindings/timer/ |
| D | mediatek,timer.yaml | 4 $id: http://devicetree.org/schemas/timer/mediatek,timer.yaml#
7 title: MediaTek SoC timers
13 MediaTek SoCs have different timers on different platforms,
22 - mediatek,mt6577-timer
23 - mediatek,mt6765-timer
24 - mediatek,mt6795-systimer
28 - mediatek,mt2701-timer
29 - mediatek,mt6580-timer
30 - mediatek,mt6582-timer
31 - mediatek,mt6589-timer
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| /Documentation/devicetree/bindings/watchdog/ |
| D | mediatek,mtk-wdt.yaml | 4 $id: http://devicetree.org/schemas/watchdog/mediatek,mtk-wdt.yaml#
7 title: MediaTek SoCs Watchdog timer
23 - mediatek,mt2712-wdt
24 - mediatek,mt6589-wdt
25 - mediatek,mt6735-wdt
26 - mediatek,mt6795-wdt
27 - mediatek,mt7986-wdt
28 - mediatek,mt7988-wdt
29 - mediatek,mt8183-wdt
30 - mediatek,mt8186-wdt
[all …]
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | mediatek,smi-larb.yaml | 2 # Copyright (c) 2020 MediaTek Inc.
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
14 The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
20 - mediatek,mt2701-smi-larb
21 - mediatek,mt2712-smi-larb
22 - mediatek,mt6779-smi-larb
23 - mediatek,mt6795-smi-larb
24 - mediatek,mt8167-smi-larb
25 - mediatek,mt8173-smi-larb
[all …]
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| D | mediatek,smi-common.yaml | 2 # Copyright (c) 2020 MediaTek Inc.
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
14 The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
16 MediaTek SMI have two generations of HW architecture, here is the list
32 - mediatek,mt2701-smi-common
33 - mediatek,mt2712-smi-common
34 - mediatek,mt6779-smi-common
35 - mediatek,mt6795-smi-common
36 - mediatek,mt8167-smi-common
[all …]
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-mt65xx.yaml | 7 title: MediaTek I2C controller
11 various MediaTek SoCs.
17 - Qii Wang <qii.wang@mediatek.com>
22 - const: mediatek,mt2712-i2c
23 - const: mediatek,mt6577-i2c
24 - const: mediatek,mt6589-i2c
25 - const: mediatek,mt7622-i2c
26 - const: mediatek,mt7981-i2c
27 - const: mediatek,mt7986-i2c
28 - const: mediatek,mt8168-i2c
[all …]
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| /Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,mmsys.yaml | 4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
7 title: MediaTek mmsys controller
13 The MediaTek mmsys system controller provides clock control, routing control,
24 - mediatek,mt2701-mmsys
25 - mediatek,mt2712-mmsys
26 - mediatek,mt6765-mmsys
27 - mediatek,mt6779-mmsys
28 - mediatek,mt6795-mmsys
29 - mediatek,mt6797-mmsys
30 - mediatek,mt8167-mmsys
[all …]
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| /Documentation/devicetree/bindings/spi/ |
| D | mediatek,spi-mt65xx.yaml | 4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
7 title: SPI Bus controller for MediaTek ARM SoCs
10 - Leilk Liu <leilk.liu@mediatek.com>
20 - mediatek,mt7629-spi
21 - mediatek,mt8365-spi
22 - const: mediatek,mt7622-spi
25 - mediatek,mt8516-spi
26 - const: mediatek,mt2712-spi
29 - mediatek,mt6779-spi
30 - mediatek,mt8186-spi
[all …]
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| /Documentation/devicetree/bindings/iommu/ |
| D | mediatek,iommu.yaml | 4 $id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
7 title: MediaTek IOMMU Architecture Implementation
10 - Yong Wu <yong.wu@mediatek.com>
13 Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
73 - mediatek,mt2701-m4u # generation one
74 - mediatek,mt2712-m4u # generation two
75 - mediatek,mt6779-m4u # generation two
76 - mediatek,mt6795-m4u # generation two
77 - mediatek,mt8167-m4u # generation two
78 - mediatek,mt8173-m4u # generation two
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| /Documentation/devicetree/bindings/soc/mediatek/ |
| D | mediatek,mutex.yaml | 4 $id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
7 title: Mediatek mutex
14 Mediatek mutex, namely MUTEX, is used to send the triggers signals called
21 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
27 - mediatek,mt2701-disp-mutex
28 - mediatek,mt2712-disp-mutex
29 - mediatek,mt6795-disp-mutex
30 - mediatek,mt8167-disp-mutex
31 - mediatek,mt8173-disp-mutex
32 - mediatek,mt8183-disp-mutex
[all …]
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | mediatek,mt2701-auxadc.yaml | 4 $id: http://devicetree.org/schemas/iio/adc/mediatek,mt2701-auxadc.yaml#
7 title: Mediatek AUXADC - ADC on Mediatek mobile SoC (mt65xx/mt81xx/mt27xx)
10 - Zhiyong Tao <zhiyong.tao@mediatek.com>
15 in some Mediatek SoCs which among other things measures the temperatures
18 directly via its own bus interface. See mediatek-thermal bindings
25 - mediatek,mt2701-auxadc
26 - mediatek,mt2712-auxadc
27 - mediatek,mt6765-auxadc
28 - mediatek,mt7622-auxadc
29 - mediatek,mt7986-auxadc
[all …]
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| /Documentation/devicetree/bindings/sound/ |
| D | mt8183-mt6358-ts3a227-max98357.txt | 4 - compatible : "mediatek,mt8183_mt6358_ts3a227_max98357" for MAX98357A codec
5 "mediatek,mt8183_mt6358_ts3a227_max98357b" for MAX98357B codec
6 "mediatek,mt8183_mt6358_ts3a227_rt1015" for RT1015 codec
7 "mediatek,mt8183_mt6358_ts3a227_rt1015p" for RT1015P codec
8 - mediatek,platform: the phandle of MT8183 ASoC platform
11 - mediatek,headset-codec: the phandles of ts3a227 codecs
12 - mediatek,ec-codec: the phandle of EC codecs.
14 - mediatek,hdmi-codec: the phandles of HDMI codec
19 compatible = "mediatek,mt8183_mt6358_ts3a227_max98357";
20 mediatek,headset-codec = <&ts3a227>;
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| /Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,ovl.yaml | 4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
7 title: Mediatek display overlay
14 Mediatek display overlay, namely OVL, can do alpha blending from
18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
25 - mediatek,mt2701-disp-ovl
26 - mediatek,mt8173-disp-ovl
27 - mediatek,mt8183-disp-ovl
28 - mediatek,mt8192-disp-ovl
29 - mediatek,mt8195-mdp3-ovl
32 - mediatek,mt7623-disp-ovl
[all …]
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