Searched +full:memory +full:- +full:controller (Results 1 – 25 of 718) sorted by relevance
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| /Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | fsl,ddr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale DDR memory controller
10 - Borislav Petkov <bp@alien8.de>
11 - York Sun <york.sun@nxp.com>
15 pattern: "^memory-controller@[0-9a-f]+$"
19 - items:
20 - enum:
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | nuvoton,npcm-memory-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton NPCM Memory Controller
10 - Marvin Lin <kflin@nuvoton.com>
11 - Stanley Chu <yschu@nuvoton.com>
14 The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction
17 The memory controller supports single bit error correction, double bit error
18 detection (in-line ECC in which a section (1/8th) of the memory device used to
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| D | nvidia,tegra210-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
15 sent from the memory controller.
19 const: nvidia,tegra210-emc
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| D | nvidia,tegra20-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SoC Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The Tegra20 Memory Controller merges request streams from various client
16 interfaces into request stream(s) for the various memory target devices,
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| D | arm,pl35x-smc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm PL35x Series Static Memory Controller (SMC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 The PL35x Static Memory Controller is a bus where you can connect two kinds
14 of memory interfaces, which are NAND and memory mapped interfaces (such as
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
26 - arm,pl353-smc-r2p1
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| D | xlnx,versal-ddrmc-edac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
14 The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
20 const: xlnx,versal-ddrmc
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| D | nvidia,tegra186-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
16 handles memory requests for 40-bit virtual addresses from internal clients
17 and arbitrates among them to allocate memory bandwidth.
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| D | snps,dw-umctl2-ddrc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
14 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
15 working with the memory devices supporting up to (LP)DDR4 protocol. It can
17 16-bits or 32-bits or 64-bits wide.
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| D | samsung,s5pv210-dmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/samsung,s5pv210-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5Pv210 SoC Dynamic Memory Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 Dynamic Memory Controller interfaces external JEDEC DDR-type SDRAM.
17 const: samsung,s5pv210-dmc
23 - compatible
24 - reg
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| D | samsung,exynos5422-dmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
9 Controller device
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Lukasz Luba <lukasz.luba@arm.com>
16 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
17 DRAM memory chips are connected. The driver is to monitor the controller in
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| D | canaan,k210-sram.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan K210 SRAM memory controller
10 The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB
11 of SRAM. The controller is initialised by the bootloader, which configures
15 - Conor Dooley <conor@kernel.org>
20 - canaan,k210-sram
25 - description: sram0 clock
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| /Documentation/devicetree/bindings/ata/ |
| D | apm-xgene.txt | 1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
4 controllers. Each SATA controller (pair of ports) have its own node.
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
12 core memory resource.
13 Third memory resource shall be the host controller
14 diagnostic memory resource.
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| /Documentation/admin-guide/cgroup-v1/ |
| D | memory.rst | 2 Memory Resource Controller
12 The Memory Resource Controller has generically been referred to as the
13 memory controller in this document. Do not confuse memory controller
14 used here with the memory controller that is used in hardware.
17 When we mention a cgroup (cgroupfs's directory) with memory controller,
18 we call it "memory cgroup". When you see git-log and source code, you'll
22 Benefits and Purpose of the memory controller
25 The memory controller isolates the memory behaviour of a group of tasks
27 uses of the memory controller. The memory controller can be used to
30 Memory-hungry applications can be isolated and limited to a smaller
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| /Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-dc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^dc@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-dc
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| /Documentation/devicetree/bindings/mips/brcm/ |
| D | soc.txt | 5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
12 The experimental -viper variants are for running Linux on the 3384's
16 ----------------
21 = Always-On control block (AON CTRL)
23 This hardware provides control registers for the "always-on" (even in low-power
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
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| /Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
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| D | aspeed-sdram-edac.txt | 3 The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
6 The memory controller supports SECDED (single bit error correction, double bit
8 every 64 bit word (effectively reducing available memory to 8/9).
10 Note, the bootloader must configure ECC mode in the memory controller.
14 - compatible: should be one of
15 - "aspeed,ast2400-sdram-edac"
16 - "aspeed,ast2500-sdram-edac"
17 - "aspeed,ast2600-sdram-edac"
18 - reg: sdram controller register set should be <0x1e6e0000 0x174>
19 - interrupts: should be AVIC interrupt #0
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| /Documentation/devicetree/bindings/dma/ |
| D | mpc512x-dma.txt | 1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
4 blocks of memory contents between memory and peripherals or
5 from memory to memory.
7 Refer to "Generic DMA Controller and DMA request bindings" in
11 - compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma";
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
14 is described in interrupt-controller/interrupts.txt file.
15 - #dma-cells: the length of the DMA specifier, must be <1>.
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| /Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
16 * Memory devices
18 The individual DRAM chips on a memory stick. These devices commonly
20 provides the number of bits that the memory controller expects:
23 * Memory Stick
25 A printed circuit board that aggregates multiple memory devices in
28 called DIMM (Dual Inline Memory Module).
30 * Memory Socket
32 A physical connector on the motherboard that accepts a single memory
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| /Documentation/gpu/amdgpu/display/ |
| D | dc-glossary.rst | 7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
39 * DCFCLK: Display Controller Fabric Clock
43 * MCLK: Memory Clock
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
62 Display Controller
68 Display Controller Engine
71 Display Controller HUB
102 Display Memory Interface
108 Display Micro-Controller Unit
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| /Documentation/arch/xtensa/ |
| D | atomctl.rst | 9 1. With and without an Coherent Cache Controller which
10 can do Atomic Transactions to the memory internally.
12 2. With and without An Intelligent Memory Controller which
19 On the FPGA Cards we typically simulate an Intelligent Memory controller
21 Memory controller we let it to the atomic operations internally while
22 doing a Cached (WB) transaction and use the Memory RCW for un-cached
25 For systems without an coherent cache controller, non-MX, we always
26 use the memory controllers RCW, though non-MX controllers likely
29 CUSTOMER-WARNING:
30 Virtually all customers buy their memory controllers from vendors that
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-edac | 3 Contact: linux-edac@vger.kernel.org
4 Description: This write-only control file will zero all the statistical
5 counters for UE and CE errors on the given memory controller.
14 Contact: linux-edac@vger.kernel.org
21 Contact: linux-edac@vger.kernel.org
22 Description: This attribute file displays the type of memory controller
27 Contact: linux-edac@vger.kernel.org
28 Description: This attribute file displays, in count of megabytes, of memory
29 that this memory controller manages.
33 Contact: linux-edac@vger.kernel.org
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,davinci-rproc.txt | 4 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
5 is used to offload some of the processor-intensive tasks or algorithms, for
8 The processor cores in the sub-system usually contain additional sub-modules
9 like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
10 controller, a dedicated local power/sleep controller etc. The DSP processor
15 Each DSP Core sub-system is represented as a single DT node.
18 --------------------
21 - compatible: Should be one of the following,
22 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
24 - reg: Should contain an entry for each value in 'reg-names'.
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| /Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,mt7622-wed.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Wireless Ethernet Dispatch Controller for MT7622
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
14 The mediatek wireless ethernet dispatch controller can be configured to
21 - enum:
22 - mediatek,mt7622-wed
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| /Documentation/admin-guide/ |
| D | cgroup-v2.rst | 1 .. _cgroup-v2:
11 conventions of cgroup v2. It describes all userland-visible aspects
12 of cgroup including core and specific controller behaviors. All
14 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`.
19 1-1. Terminology
20 1-2. What is cgroup?
22 2-1. Mounting
23 2-2. Organizing Processes and Threads
24 2-2-1. Processes
25 2-2-2. Threads
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