Searched +full:meson8 +full:- +full:ddr +full:- +full:clkc (Results 1 – 2 of 2) sorted by relevance
| /Documentation/devicetree/bindings/clock/ |
| D | amlogic,meson8-ddr-clkc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic DDR Clock Controller
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
15 - amlogic,meson8-ddr-clkc
16 - amlogic,meson8b-ddr-clkc
24 clock-names:
26 - const: xtal
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| D | amlogic,meson8b-clkc.txt | 1 * Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
3 The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
8 - compatible: must be one of:
9 - "amlogic,meson8-clkc" for Meson8 (S802) SoCs
10 - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
11 - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
14 - clocks: list of clock phandles, one for each entry in clock-names
15 - clock-names: should contain the following:
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