Home
last modified time | relevance | path

Searched +full:mipi +full:- +full:mode (Results 1 – 25 of 45) sorted by relevance

12

/Documentation/devicetree/bindings/phy/
Dmixel,mipi-dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
[all …]
Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
21 'tx-p2p-microvolt-names' property must be provided and contain
22 corresponding mode names.
[all …]
Dstarfive,jh7110-dphy-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive SoC JH7110 MIPI D-PHY Rx Controller
10 - Jack Zhu <jack.zhu@starfivetech.com>
11 - Changhuang Liang <changhuang.liang@starfivetech.com>
14 StarFive SoCs contain a MIPI CSI D-PHY based on M31 IP, used to
19 const: starfive,jh7110-dphy-rx
26 - description: config clock
[all …]
/Documentation/devicetree/bindings/display/panel/
Dpanel-mipi-dbi-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPI DBI SPI Panel
10 - Noralf Trønnes <noralf@tronnes.org>
13 This binding is for display panels using a MIPI DBI compatible controller
14 in SPI mode.
16 The MIPI Alliance Standard for Display Bus Interface defines the electrical
23 - Power:
[all …]
Dsitronix,st7701.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jagan Teki <jagan@amarulasolutions.com>
15 several system interfaces like MIPI/RGB/SPI.
17 Techstar TS8550B is 480x854, 2-lane MIPI DSI LCD panel which has
20 Densitron DMT028VGHMCMI-1A is 480x640, 2-lane MIPI DSI LCD panel
21 which has built-in ST7701 chip.
26 - enum:
27 - anbernic,rg-arc-panel
[all …]
Dorisetech,otm8009a.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode)
10 - Philippe CORNU <philippe.cornu@foss.st.com>
14 a MIPI-DSI video interface. Its backlight is managed through the DSI link.
16 - $ref: panel-common.yaml#
27 enable-gpios: true
29 power-supply: true
31 reset-gpios:
[all …]
/Documentation/devicetree/bindings/display/bridge/
Dsamsung,mipi-dsim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung MIPI DSIM bridge controller
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
15 Samsung MIPI DSIM bridge controller can be found it on Exynos
21 - enum:
[all …]
Dfsl,imx93-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx93-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX93 specific extensions to Synopsys Designware MIPI DSI
10 - Liu Ying <victor.liu@nxp.com>
13 There is a Synopsys Designware MIPI DSI Host Controller and a Synopsys
14 Designware MIPI DPHY embedded in Freescale i.MX93 SoC. Some configurations
15 and extensions to them are controlled by i.MX93 media blk-ctrl.
18 - $ref: snps,dw-mipi-dsi.yaml#
[all …]
Drenesas,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L MIPI DSI Encoder
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This binding describes the MIPI DSI encoder embedded in the Renesas
14 RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
18 - $ref: /schemas/display/dsi-controller.yaml#
23 - enum:
24 - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
[all …]
Dnwl-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
10 - Guido Gúnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com>
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
[all …]
Drenesas,dsi-csi2-tx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car MIPI DSI/CSI-2 Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
14 R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
20 - renesas,r8a779a0-dsi-csi2-tx # for V3U
21 - renesas,r8a779g0-dsi-csi2-tx # for V4H
[all …]
/Documentation/devicetree/bindings/media/
Dvideo-interfaces.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
49 specify #address-cells, #size-cells properties independently for the 'port'
[all …]
Dmicrochip,xisc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Eugen Hristev <eugen.hristev@microchip.com>
25 const: microchip,sama7g5-isc
36 clock-names:
38 - const: hclock
40 '#clock-cells':
43 clock-output-names:
44 const: isc-mck
[all …]
Dcdns,csi2tx.txt1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
13 * esc_clk: escape mode clock
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
[all …]
/Documentation/devicetree/bindings/soc/samsung/
Dexynos-pmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
18 - google,gs101-pmu
19 - samsung,exynos3250-pmu
20 - samsung,exynos4210-pmu
21 - samsung,exynos4212-pmu
22 - samsung,exynos4412-pmu
[all …]
/Documentation/devicetree/bindings/media/i2c/
Dovti,ov02a10.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dongchun Zhu <dongchun.zhu@mediatek.com>
13 description: |-
14 The Omnivision OV02A10 is a low-cost, high performance, 1/5-inch, 2 megapixel
17 @ 1600x1200 (UXGA) resolution transferred over a 1-lane MIPI interface. The
18 sensor output is available via CSI-2 serial data output.
21 - $ref: /schemas/media/video-interface-devices.yaml#
33 clock-names:
[all …]
Dthine,thp7312.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Elder <paul.elder@@ideasonboard.com>
17 MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2
18 or parallel. The hardware is capable of transmitting and receiving MIPI
23 - $ref: /schemas/media/video-interface-devices.yaml#
36 thine,boot-mode:
42 Boot mode of the THP7312, reflecting the value of the BOOT[0] pin strap.
43 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from
[all …]
Dmaxim,max96717.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MAX96717 CSI-2 to GMSL2 Serializer
11 - Julien Massot <julien.massot@collabora.com>
14 The MAX96717 serializer converts MIPI CSI-2 D-PHY formatted input
16 simultaneously transmit bidirectional control-channel data while forward
18 remotely located deserializer using industry-standard coax or STP
19 interconnects. The device cans operate in pixel or tunnel mode. In pixel mode
20 the MAX96717 can select the MIPI datatype, while the tunnel mode forward all the MIPI
[all …]
Dmaxim,max96714.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Maxim MAX96714 GMSL2 to CSI-2 Deserializer
11 - Julien Massot <julien.massot@collabora.com>
14 The MAX96714 deserializer converts GMSL2 serial inputs into MIPI
15 CSI-2 D-PHY formatted output. The device allows the GMSL2 link to
16 simultaneously transmit bidirectional control-channel data while forward
18 remotely located serializer using industry-standard coax or STP
19 interconnects. The device cans operate in pixel or tunnel mode. In pixel mode
[all …]
/Documentation/devicetree/bindings/soundwire/
Dqcom,soundwire.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
19 - qcom,soundwire-v1.3.0
20 - qcom,soundwire-v1.5.0
21 - qcom,soundwire-v1.5.1
22 - qcom,soundwire-v1.6.0
23 - qcom,soundwire-v1.7.0
[all …]
/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,csi2rxss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@amd.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
[all …]
/Documentation/admin-guide/media/
Dimx.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ------------
15 - Image DMA Controller (IDMAC)
16 - Camera Serial Interface (CSI)
17 - Image Converter (IC)
18 - Sensor Multi-FIFO Controller (SMFC)
19 - Image Rotator (IRT)
20 - Video De-Interlacing or Combining Block (VDIC)
26 re-ordering (for example UYVY to YUYV) within the same colorspace, and
27 packed <--> planar conversion. The IDMAC can also perform a simple
[all …]
/Documentation/driver-api/soundwire/
Dsummary.rst5 SoundWire is a new interface ratified in 2015 by the MIPI Alliance.
10 SoundWire is a 2-pin multi-drop interface with data and clock line. It
15 commands over a single two-pin interface.
23 (4) Device status monitoring, including interrupt-style alerts to the Master.
30 transmit or receiving mode (typically fixed direction but configurable
38 +---------------+ +---------------+
40 | Master |-------+-------------------------------| Slave |
42 | |-------|-------+-----------------------| |
43 +---------------+ | | +---------------+
47 +--+-------+--+
[all …]
/Documentation/driver-api/media/
Dtx-rx.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. _transmitter-receiver:
10 CSI-2 receiver in an SoC.
13 ---------
17 MIPI CSI-2
20 CSI-2 is a data bus intended for transferring images from cameras to
21 the host SoC. It is defined by the `MIPI alliance`_.
23 .. _`MIPI alliance`: https://www.mipi.org/
32 .. _`BT.656`: https://en.wikipedia.org/wiki/ITU-R_BT.656
35 -------------------
[all …]
/Documentation/driver-api/i3c/
Dprotocol.rst1 .. SPDX-License-Identifier: GPL-2.0
15 it brings to the table. If you need more information, please refer to the MIPI
17 https://resources.mipi.org/mipi-i3c-v1-download).
22 The I3C (pronounced 'eye-three-see') is a MIPI standardized protocol designed
25 while remaining power-efficient.
42 I3C is a multi-master protocol, so there might be several masters on a bus,
51 In addition to these per-device addresses, the protocol defines a broadcast
70 * BCR: Bus Characteristic Register. This 8-bit register describes the device bus
72 * DCR: Device Characteristic Register. This 8-bit register describes the
74 * Provisioned ID: A 48-bit unique identifier. On a given bus there should be no
[all …]

12