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Searched +full:mmcc +full:- +full:msm8960 (Results 1 – 4 of 4) sorted by relevance

/Documentation/devicetree/bindings/clock/
Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
[all …]
/Documentation/devicetree/bindings/display/msm/
Dmdp4.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 MDP4 display controller found in SoCs like MSM8960, APQ8064 and MSM8660.
13 - Rob Clark <robdclark@gmail.com>
23 clock-names:
25 - const: core_clk
26 - const: iface_clk
27 - const: bus_clk
28 - const: lut_clk
[all …]
/Documentation/devicetree/bindings/iommu/
Dqcom,apq8064-iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - David Heidelberg <david@ixit.cz>
16 outside of the CPU, each connected to the IOMMU through a port called micro-TLB.
20 const: qcom,apq8064-iommu
24 - description: interface clock for register accesses
25 - description: functional clock for bus accesses
27 clock-names:
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/Documentation/devicetree/bindings/arm/
Dqcom-soc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/qcom-soc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
15 qcom,SoC-IP
18 qcom,sdm845-llcc-bwmon
26 pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
28 - compatible
34 - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
[all …]