Searched +full:mmu +full:- +full:type (Results 1 – 25 of 42) sorted by relevance
12
| /Documentation/arch/xtensa/ |
| D | booting.rst | 7 tag value constants. First entry in the list must have type BP_TAG_FIRST, last
8 entry must have type BP_TAG_LAST. The address of the first list entry is
9 passed to the kernel in the register a2. The address type depends on MMU type:
11 - For configurations without MMU, with region protection or with MPU the
13 - For configurations with region translarion MMU or with MMUv3 and CONFIG_MMU=n
16 - For configurations with MMUv2 the address must be a virtual address in the
18 - For configurations with MMUv3 and CONFIG_MMU=y the address may be either a
|
| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
[all …]
|
| /Documentation/virt/kvm/ |
| D | locking.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ---------------------
12 - cpus_read_lock() is taken outside kvm_lock
14 - kvm_usage_lock is taken outside cpus_read_lock()
16 - kvm->lock is taken outside vcpu->mutex
18 - kvm->lock is taken outside kvm->slots_lock and kvm->irq_lock
20 - kvm->slots_lock is taken outside kvm->irq_lock, though acquiring
23 - kvm->mn_active_invalidate_count ensures that pairs of
25 use the same memslots array. kvm->slots_lock and kvm->slots_arch_lock
26 are taken on the waiting side when modifying memslots, so MMU notifiers
[all …]
|
| /Documentation/virt/kvm/x86/ |
| D | mmu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 The x86 kvm shadow mmu
7 The mmu (in arch/x86/kvm, files mmu.[ch] and paging_tmpl.h) is responsible
8 for presenting a standard x86 mmu to the guest, while translating guest
11 The mmu code attempts to satisfy the following requirements:
13 - correctness:
15 on an emulated mmu except for timing (we attempt to comply
18 - security:
21 - performance:
22 minimize the performance penalty imposed by the mmu
[all …]
|
| /Documentation/devicetree/bindings/iommu/ |
| D | arm,smmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
[all …]
|
| /Documentation/devicetree/bindings/gpu/ |
| D | arm,mali-valhall-csf.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-valhall-csf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liviu Dudau <liviu.dudau@arm.com>
11 - Boris Brezillon <boris.brezillon@collabora.com>
15 pattern: '^gpu@[a-f0-9]+$'
19 - items:
20 - enum:
21 - rockchip,rk3588-mali
[all …]
|
| D | arm,mali-midgard.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-midgard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 pattern: '^gpu@[a-f0-9]+$'
17 - items:
18 - enum:
19 - samsung,exynos5250-mali
20 - const: arm,mali-t604
[all …]
|
| D | arm,mali-utgard.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
11 - Maxime Ripard <mripard@kernel.org>
12 - Heiko Stuebner <heiko@sntech.de>
16 pattern: '^gpu@[a-f0-9]+$'
19 - items:
20 - const: allwinner,sun8i-a23-mali
[all …]
|
| /Documentation/driver-api/media/drivers/ |
| D | ipu6.rst | 1 .. SPDX-License-Identifier: GPL-2.0
34 ------------------------
51 ---------
61 -------------------------------------
76 -----------------
80 Buttress with a copy of the SoC time, this counter maintains the up-to-date time
86 DMA and MMU
90 32-bit virtual address space. The IPU6 has MMU address translation hardware to
94 IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU
95 register and allows MMU to perform page table lookups.
[all …]
|
| /Documentation/gpu/ |
| D | drm-vm-bind-locking.rst | 1 .. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
30 meta-data. Typically one per client (DRM file-private), or one per
33 associated meta-data. The backing storage of a gpu_vma can either be
34 a GEM object or anonymous or page-cache pages mapped also into the CPU
40 is anonymous or page-cache pages as described above.
43 page-table entries point to that backing store.
47 the :doc:`dma-buf doc </driver-api/dma-buf>`.
52 additional dma_fences to the dma_resv. The lock is of a type that
53 allows deadlock-safe locking of multiple dma_resvs in arbitrary
55 :doc:`dma-buf doc </driver-api/dma-buf>`.
[all …]
|
| /Documentation/arch/powerpc/ |
| D | booting.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ------------------
9 bootloader <-> kernel interfaces, in order to avoid the degeneration that had
14 merged architecture for ppc32 and ppc64, new 32-bit platforms and 32-bit
19 of a device-tree whose format is defined after Open Firmware specification.
21 doesn't require the device-tree to represent every device in the system and only
47 bindings to powerpc. Only the 32-bit client interface
52 The MMU is either on or off; the kernel will run the
54 extract the device-tree and other information from open
55 firmware and build a flattened device-tree as described
[all …]
|
| D | cxl.rst | 28 +----------+ +---------+
34 +----------+ +---------+
36 | +------+ | PSL |
37 | | CAPP |<------>| |
38 +---+------+ PCIE +---------+
65 - POWER8 and PSL Version 8 are compliant to the CAIA Version 1.0.
66 - POWER9 and PSL Version 9 are compliant to the CAIA Version 2.0.
70 * Interaction with the nest MMU on the P9 chip.
85 When using dedicated mode only one MMU context is supported. In
123 The WED is a 64-bit parameter passed to the AFU when a context is
[all …]
|
| /Documentation/arch/arm/ |
| D | interrupts.rst | 5 2.5.2-rmk5:
7 major architecture-specific subsystems.
10 MMU TLB. Each MMU TLB variant is now handled completely separately -
21 machine type that we currently have.
26 SA1100 ------------> Neponset -----------> SA1111
28 -----------> USAR
30 -----------> SMC9196
33 exclusive of each other - if you're processing one interrupt from the
36 IDE PIO-based interrupt on the SA1111 excludes all other SA1111 and
37 SMC9196 interrupts until it has finished transferring its multi-sector
[all …]
|
| D | booting.rst | 9 The following documentation is relevant to 2.4.18-rmk6 and beyond.
21 3. Detect the machine type.
28 ---------------------------
44 -----------------------------
60 Documentation/admin-guide/kernel-parameters.rst.
63 3. Detect the machine type
64 --------------------------
69 MANDATORY except for DT-only platforms
71 The boot loader should detect the machine type its running on by some
75 value to the kernel. (see linux/arch/arm/tools/mach-types). This
[all …]
|
| /Documentation/mm/ |
| D | page_tables.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 feature of all Unix-like systems as time went by. In 1985 the feature was
34 As you can see, with 4KB pages the page base address uses bits 12-31 of the
42 this single table were referred to as *PTE*:s - page table entries.
57 megabytes or even gigabytes in a single high-level page table entry, taking
63 +-----+
65 +-----+
67 | +-----+
68 +-->| P4D |
69 +-----+
[all …]
|
| D | hmm.rst | 5 Provide infrastructure and helpers to integrate non-conventional memory (device
21 CPU page-table mirroring works and the purpose of HMM in this context. The
52 complex data set needs to re-map all the pointer relations between each of its
95 two-way cache coherency between CPU and device and allow all atomic operations the
115 allocate a buffer (or use a pool of pre-allocated buffers) and write GPU
155 During the ops->invalidate() callback the device driver must perform the
164 It will trigger a page fault on missing or read-only entries if write access is
178 if (!mmget_not_zero(interval_sub->notifier.mm))
179 return -EFAULT;
187 if (ret == -EBUSY)
[all …]
|
| /Documentation/driver-api/ |
| D | device_link.rst | 57 device ``->probe`` callback or a boot-time PCI quirk.
61 ``->probe`` callback while the supplier hasn't started to probe yet: Had the
65 non-presence. [Note that it is valid to create a link from the consumer's
66 ``->probe`` callback while the supplier is still probing, but the consumer must
72 is added in the ``->probe`` callback of the supplier or consumer driver, it is
73 typically deleted in its ``->remove`` callback for symmetry. That way, if the
87 link is added from the consumer's ``->probe`` callback: ``DL_FLAG_RPM_ACTIVE``
93 Similarly, when the device link is added from supplier's ``->probe`` callback,
125 :c:func:`device_link_add()` may cause the PM-runtime usage counter of the
129 called twice in a row for the same consumer-supplier pair without removing the
[all …]
|
| /Documentation/ABI/testing/ |
| D | debugfs-driver-habanalabs | 46 the generic Linux user-space PCI mapping) because the DDR bar
61 the generic Linux user-space PCI mapping) because the DDR bar
77 Linux user-space PCI mapping) because the amount of internal
212 What: /sys/kernel/debug/accel/<parent_device>/mmu
220 echo "1 0x1000" > /sys/kernel/debug/accel/<parent_device>/mmu
226 Description: Check and display page fault or access violation mmu errors for
228 e.g. to display error info for MMU hw cap bit 9, you need to do:
241 Linux user-space PCI mapping) because this space is protected
260 Description: Exposes the device's server type, maps to enum hl_server_type.
286 next read would return X+1-st newest state dump.
[all …]
|
| /Documentation/accel/ |
| D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 accelerators in a common way to user-space and provide a common set of
11 These devices can be either stand-alone ASICs or IP blocks inside an SoC/GPU.
13 Machine-Learning (ML) and/or Deep-Learning (DL) computations, the accel layer
19 - Edge AI - doing inference at an edge device. It can be an embedded ASIC/FPGA,
23 - Inference data-center - single/multi user devices in a large server. This
24 type of device can be stand-alone or an IP inside a SoC or a GPU. It will
25 have on-board DRAM (to hold the DL topology), DMA engines and
26 command submission queues (either kernel or user-space queues).
27 It might also have an MMU to manage multiple users and might also enable
[all …]
|
| /Documentation/misc-devices/ |
| D | uacce.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ---------------------
6 Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
29 | MMU | | IOMMU |
42 ------------
51 FIFO-like interface. And it maintains a unified address space between the
58 | WarpDrive library | ------------> | user driver |
77 ------------- | Device Driver | | IOMMU | |
83 -------------------------- | Device(Hardware) |
88 ----------------
[all …]
|
| /Documentation/translations/zh_CN/mm/ |
| D | hmm.rst | 1 .. include:: ../disclaimer-zh_CN.rst
124 在 ops->invalidate() 回调期间，设备驱动程序必须对范围执行更新操作（将范围标记为只
150 if (!mmget_not_zero(interval_sub->notifier.mm))
151 return -EFAULT;
159 if (ret == -EBUSY)
165 take_lock(driver->update);
167 release_lock(driver->update);
174 release_lock(driver->update);
178 driver->update 锁与驱动程序在其 invalidate() 回调中使用的锁相同。该锁必须在调用
189 range->default_flags = HMM_PFN_REQ_FAULT;
[all …]
|
| /Documentation/arch/sparc/ |
| D | adi.rst | 20 addresses ADI is being enabled on. MMU checks the version tag only
33 bits of the virtual address being presented to the MMU. For example on
34 SPARC M7 processor, MMU uses bits 63-60 for version tags and ADI block
37 virtual addresses that contain 0xa in bits 63-60.
58 - Version tag values of 0x0 and 0xf are reserved. These values match any
61 - Version tags are set on virtual addresses from userspace even though
66 - When a task frees a memory page it had set version tags on, the page
67 goes back to free page pool. When this page is re-allocated to a task,
73 - ADI tag mismatches are not detected for non-faulting loads.
75 - Kernel does not set any tags for user pages and it is entirely a
[all …]
|
| /Documentation/virt/kvm/arm/ |
| D | pkvm.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 ------------
9 Protected KVM (pKVM) is a KVM/arm64 extension which uses the two-stage
10 translation capability of the Armv8 MMU to isolate guest memory from the host
12 without relying on whizz-bang features in hardware, but still allowing room for
13 complementary technologies such as memory encryption and hardware-backed
19 introduced to manage manipulation of guest stage-2 page tables, creation of VM
22 at stage-2, providing the hypervisor code with a mechanism to restrict host
26 -------------
29 "``kvm-arm.mode=protected``" on the command-line. Once enabled, VMs can be spawned
[all …]
|
| /Documentation/translations/zh_TW/arch/arm/ |
| D | Booting | 11 ---------------------------------------------------------------------
24 ---------------------------------------------------------------------
32 以下文檔適用於 2.4.18-rmk6 及以上版本。
42 3、檢測機器的類型（machine type）。
48 -------------------
60 -----------------------------
71 Documentation/admin-guide/kernel-parameters.rst。
75 --------------------------
83 (詳見 linux/arch/arm/tools/mach-types )。
86 ------------------
[all …]
|
| /Documentation/translations/zh_CN/arch/arm/ |
| D | Booting | 11 ---------------------------------------------------------------------
24 ---------------------------------------------------------------------
32 以下文档适用于 2.4.18-rmk6 及以上版本。
42 3、检测机器的类型（machine type）。
48 -------------------
60 -----------------------------
71 Documentation/admin-guide/kernel-parameters.rst。
75 --------------------------
83 (详见 linux/arch/arm/tools/mach-types )。
86 ------------------
[all …]
|
12