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| /Documentation/networking/devlink/ |
| D | devlink-eswitch-attr.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Devlink E-Switch Attribute
7 Devlink E-Switch supports two modes of operation: legacy and switchdev.
8 Legacy mode operates based on traditional MAC/VLAN steering rules. Switching
9 decisions are made based on MAC addresses, VLANs, etc. There is limited ability
12 On the other hand, switchdev mode allows for more advanced offloading
13 capabilities of the E-Switch to hardware. In switchdev mode, more switching
16 or scalable-functions (SFs) of the device. See more information about
20 In addition, the devlink E-Switch also comes with other attributes listed
26 The following is a list of E-Switch attributes.
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| /Documentation/dev-tools/ |
| D | kasan.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 --------
11 designed to find out-of-bounds and use-after-free bugs.
16 2. Software Tag-Based KASAN
17 3. Hardware Tag-Based KASAN
19 Generic KASAN, enabled with CONFIG_KASAN_GENERIC, is the mode intended for
20 debugging, similar to userspace ASan. This mode is supported on many CPU
23 Software Tag-Based KASAN or SW_TAGS KASAN, enabled with CONFIG_KASAN_SW_TAGS,
25 This mode is only supported for arm64, but its moderate memory overhead allows
26 using it for testing on memory-restricted devices with real workloads.
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| /Documentation/ABI/testing/ |
| D | sysfs-class-net-qmi | 9 framing from '802.3' to 'raw-ip'.
12 mode. The netdev is an ordinary ethernet device in
13 '802.3' mode, and the driver expects to exchange
15 netdev is a headerless p-t-p device in 'raw-ip' mode,
22 link framing mode, changing this setting to 'Y' if the
23 firmware is configured for 'raw-ip' mode.
33 based network device, supported by recent Qualcomm based
50 created qmap mux based network device.
69 Set this to 'Y' to enable 'pass-through' mode, allowing packets
75 'Pass-through' mode can be enabled when the device is in
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| D | sysfs-driver-fsi-master-gpio | 1 What: /sys/bus/platform/devices/[..]/fsi-master-gpio/external_mode
6 Controls access arbitration for GPIO-based FSI master. A
7 value of 0 (the default) sets normal mode, where the
8 driver performs FSI bus transactions, 1 sets external mode,
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| D | sysfs-driver-intc_sar | 7 Specific Absorption Rate (SAR) regulatory mode is typically
8 derived based on information like mcc (Mobile Country Code) and
11 the current SAR regulatory mode on the Dynamic SAR driver using
13 this sysfs node, the currently configured regulatory mode value
23 - The regulatory mode value has one of the above values.
24 - The default regulatory mode used in the driver is 0.
36 - device_mode
37 - bandtable_index
38 - antennatable_index
39 - sartable_index
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| D | sysfs-class-power-wilco | 1 What: /sys/class/power_supply/wilco-charger/charge_type
10 Battery settings adaptively optimized based on
24 On Wilco device this mode is pre-configured in the factory
25 through EC's private PID. Switching to a different mode will
26 be denied by Wilco EC when Long Life mode is enabled.
28 What: /sys/class/power_supply/wilco-charger/charge_control_start_threshold
35 What: /sys/class/power_supply/wilco-charger/charge_control_end_threshold
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| D | sysfs-block-dm | 1 What: /sys/block/dm-<num>/dm/name
4 Contact: dm-devel@redhat.com
5 Description: Device-mapper device name.
6 Read-only string containing mapped device name.
7 Users: util-linux, device-mapper udev rules
9 What: /sys/block/dm-<num>/dm/uuid
12 Contact: dm-devel@redhat.com
13 Description: Device-mapper device UUID.
14 Read-only string containing DM-UUID or empty string
15 if DM-UUID is not set.
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| /Documentation/input/devices/ |
| D | edt-ft5x06.rst | 1 EDT ft5x06 based Polytouch devices
2 ----------------------------------
4 The edt-ft5x06 driver is useful for the EDT "Polytouch" family of capacitive
5 touch screens. Note that it is *not* suitable for other devices based on the
6 focaltec ft5x06 devices, since they contain vendor-specific firmware. In
18 allows setting the "click"-threshold in the range from 0 to 80.
36 (readonly) contains the number of sensor fields in X- and
37 Y-direction.
39 mode:
40 allows switching the sensor between "factory mode" and "operation
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| /Documentation/devicetree/bindings/ |
| D | common-properties.txt | 5 ----------
13 - big-endian: Boolean; force big endian register accesses
15 know the peripheral always needs to be accessed in big endian (BE) mode.
16 - little-endian: Boolean; force little endian register accesses
18 peripheral always needs to be accessed in little endian (LE) mode.
19 - native-endian: Boolean; always use register accesses matched to the
20 endianness of the kernel binary (e.g. LE vmlinux -> readl/writel,
21 BE vmlinux -> ioread32be/iowrite32be). In this case no byte swaps
22 will ever be performed. Use this if the hardware "self-adjusts"
23 register endianness based on the CPU's configured endianness.
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| /Documentation/networking/device_drivers/ethernet/cirrus/ |
| D | cs89x0.rst | 1 .. SPDX-License-Identifier: GPL-2.0
33 2.1 CS8900-based Adapter Configuration
34 2.2 CS8920-based Adapter Configuration
40 4.2 Compiling the driver to support memory mode
46 5.2.1 Diagnostic Self-Test
66 The CS8900-based ISA Ethernet Adapters from Cirrus Logic follow
67 IEEE 802.3 standards and support half or full-duplex operation in ISA bus
69 in 16-bit ISA or EISA bus expansion slots and are available in
70 10BaseT-only or 3-media configurations (10BaseT, 10Base2, and AUI for 10Base-5
73 CS8920-based adapters are similar to the CS8900-based adapter with additional
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| /Documentation/devicetree/bindings/mtd/ |
| D | davinci-nand.txt | 7 Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
8 Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
12 - compatible: "ti,davinci-nand"
13 "ti,keystone-nand"
15 - reg: Contains 2 offset/length values:
16 - offset and length for the access window.
17 - offset and length for accessing the AEMIF
20 - ti,davinci-chipselect: number of chipselect. Indicates on the
23 Can be in the range [0-3].
27 - ti,davinci-mask-ale: mask for ALE. Needed for executing address
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| /Documentation/driver-api/backlight/ |
| D | lp855x-driver.rst | 15 -----------
26 Backlight control mode.
28 Value: pwm based or register based
37 ------------------------
49 Only valid when brightness is pwm input mode.
58 1) lp8552 platform data: i2c register mode with new eeprom data::
68 .name = "lcd-bl",
75 2) lp8556 platform data: pwm input mode with default rom data::
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| /Documentation/devicetree/bindings/net/ |
| D | microchip,sparx5-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanced TCAM-based VLAN and
17 security through TCAM-based frame processing using versatile content
25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
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| D | smsc-lan87xx.txt | 8 - clocks:
12 - smsc,disable-energy-detect:
13 If set, do not enable energy detect mode for the SMSC phy.
14 default: enable energy detect mode
17 smsc phy with disabled energy detect mode on an am335x based board.
19 pinctrl-names = "default", "sleep";
20 pinctrl-0 = <&davinci_mdio_default>;
21 pinctrl-1 = <&davinci_mdio_sleep>;
23 ethernetphy0: ethernet-phy@0 {
25 smsc,disable-energy-detect;
|
| D | qcom,qca807x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
21 Both models have a combo port that supports 1000BASE-X and
22 100BASE-FX fiber.
25 output only pins that natively drive LED-s for up to 2 attached
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| D | microchip,lan966x-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
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| /Documentation/arch/x86/x86_64/ |
| D | fsgs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 memory can use segment register based addressing mode. The following
10 Segment-register:Byte-address
12 The segment base address is added to the Byte-address to compute the
14 instances of data with the identical Byte-address, i.e. the same code. The
15 selection of a particular instance is purely based on the base-address in
18 In 32-bit mode the CPU provides 6 segments, which also support segment
21 In 64-bit mode the CS/SS/DS/ES segments are ignored and the base address is
23 still functional in 64-bit mode.
26 ------------------------------
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| /Documentation/devicetree/bindings/power/reset/ |
| D | reboot-mode.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/reboot-mode.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic reboot mode core map
10 - Andy Yan <andy.yan@rock-chips.com>
13 This driver get reboot mode arguments and call the write
18 All mode properties are vendor specific, it is a indication to tell
20 as mode-xxx = <magic> (xxx is mode name, magic should be a non-zero value).
23 - normal: Normal reboot mode, system reboot with command "reboot".
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| /Documentation/devicetree/bindings/spi/ |
| D | brcm,bcm63xx-hsspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Zhang <william.zhang@broadcom.com>
11 - Kursad Oney <kursad.oney@broadcom.com>
12 - Jonas Gorski <jonas.gorski@gmail.com>
16 early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0
17 controller was carried over to recent ARM based chips, such as BCM63138,
18 BCM4908 and BCM6858. The old MIPS based chip should continue to use the
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| /Documentation/admin-guide/mm/ |
| D | numa_memory_policy.rst | 10 supported platforms with Non-Uniform Memory Access architectures since 2.4.?.
16 (``Documentation/admin-guide/cgroup-v1/cpusets.rst``)
19 programming interface that a NUMA-aware application can take advantage of. When
28 ------------------------
41 not to overload the initial boot node with boot-time
45 this is an optional, per-task policy. When defined for a
61 In a multi-threaded task, task policies apply only to the thread
69 changes its task policy remain where they were allocated based on
98 mapping-- i.e., at Copy-On-Write.
101 virtual address space--a.k.a. threads--independent of when
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| /Documentation/virt/hyperv/ |
| D | clocks.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 -----
8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
12 architectural system counter is functional in guest VMs on Hyper-V.
13 While Hyper-V also provides a synthetic system clock and four synthetic
14 per-CPU timers as described in the TLFS, they are not used by the
15 Linux kernel in a Hyper-V guest on arm64. However, older versions
16 of Hyper-V for arm64 only partially virtualize the ARMv8
19 Linux kernel versions on these older Hyper-V versions requires an
20 out-of-tree patch to use the Hyper-V synthetic clocks/timers instead.
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| /Documentation/devicetree/bindings/mfd/ |
| D | gateworks-gsc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Watchdog Timer
15 - GPIO
16 - Pushbutton controller
17 - Hardware monitor with ADC's for temperature and voltage rails and
21 - Tim Harvey <tharvey@gateworks.com>
25 pattern: "gsc@[0-9a-f]{1,2}"
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | intel,ce4100-lapic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
28 [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
32 const: intel,ce4100-lapic
37 interrupt-controller: true
39 '#interrupt-cells':
42 intel,virtual-wire-mode:
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| /Documentation/hwmon/ |
| D | tc654.rst | 13 - Chris Packham <chris.packham@alliedtelesis.co.nz>
14 - Masahiko Iwamoto <iwamoto@allied-telesis.co.jp>
17 -----------
20 The TC654 uses the 2-wire interface compatible with the SMBUS 2.0
25 -------------------
27 mode. However, for this chip the output is always pwm, and the
32 Setting pwm1_mode to 1 will cause the pwm output to be driven based on
34 driven based on the Vin input.
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| /Documentation/fb/ |
| D | tgafb.rst | 5 This is a driver for DECChip 21030 based graphics framebuffers, a.k.a. TGA
9 - ZLxP-E1 (8bpp, 2 MB VRAM)
10 - ZLxP-E2 (32bpp, 8 MB VRAM)
11 - ZLxP-E3 (32bpp, 16 MB VRAM, Zbuffer)
14 Uytterhoeven, which was based on the original TGA console code written by
20 * Support for fixed-frequency and other oddball monitors
21 (by allowing the video mode to be set at boot time)
23 User-visible changes since Linux 2.2.x:
25 * Sync-on-green is now handled properly
47 mode:X default video mode. The following video modes are supported:
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