Searched full:mpcore (Results 1 – 8 of 8) sorted by relevance
| /Documentation/devicetree/bindings/arm/marvell/ |
| D | armada-380-mpcore-soc-ctrl.txt | 1 Marvell Armada 38x CA9 MPcore SoC Controller
6 - compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
9 datasheet for the CA9 MPcore SoC Control registers
11 mpcore-soc-ctrl@20d20 {
12 compatible = "marvell,armada-380-mpcore-soc-ctrl";
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,scu.yaml | 13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
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| D | arm,realview.yaml | 15 earlier CPUs such as TrustZone and multicore (MPCore).
32 - description: ARM RealView Platform Baseboard for ARM 11 MPCore
34 multiprocessing with ARM11 using MPCore using symmetric
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| D | arm,vexpress-juno.yaml | 46 in MPCore configuration in a test chip on the core tile. See ARM
58 cores in a MPCore configuration in a test chip on the core tile. See
71 CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
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| D | cpus.yaml | 51 On ARM 11 MPcore based systems this property is
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| /Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.yaml | 252 interrupts = <0 65 0x04>, /* mpcore syncpt */
253 <0 67 0x04>; /* mpcore general */
388 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
389 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
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| /Documentation/arch/arm/keystone/ |
| D | overview.rst | 7 Keystone range of SoCs are based on ARM Cortex-A15 MPCore Processors
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | xlnx,zynqmp-r5fss.yaml | 42 The RPU MPCore can operate in split mode (Dual-processor performance), Safety
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