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Searched +full:mpfs +full:- +full:clock (Results 1 – 10 of 10) sorted by relevance

/Documentation/devicetree/bindings/spi/
Dmicrochip,mpfs-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Conor Dooley <conor.dooley@microchip.com>
19 - items:
20 - enum:
21 - microchip,mpfs-qspi
22 - microchip,pic64gx-qspi
23 - const: microchip,coreqspi-rtl-v2
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/Documentation/devicetree/bindings/clock/
Dmicrochip,mpfs-clkcfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire Clock Control Module
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
17 user nodes by the CLKCFG node phandle and the clock index in the group, from
22 const: microchip,mpfs-clkcfg
26 - description: |
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Dmicrochip,mpfs-ccc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
10 - Conor Dooley <conor.dooley@microchip.com>
13 Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
20 const: microchip,mpfs-ccc
24 - description: PLL0's control registers
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/Documentation/devicetree/bindings/rtc/
Dmicrochip,mfps-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip PolarFire Soc (MPFS) RTC
11 - $ref: rtc.yaml#
14 - Daire McNamara <daire.mcnamara@microchip.com>
15 - Lewis Hanly <lewis.hanly@microchip.com>
20 - microchip,mpfs-rtc
27 - description: |
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/Documentation/devicetree/bindings/usb/
Dmicrochip,mpfs-musb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip MPFS USB Controller
10 - $ref: usb-drd.yaml#
13 - Conor Dooley <conor.dooley@microchip.com>
18 - microchip,mpfs-musb
29 interrupt-names:
31 - const: dma
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/Documentation/devicetree/bindings/net/can/
Dmicrochip,mpfs-can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/microchip,mpfs-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Microchip PolarFire SoC (MPFS) can controller
11 - Conor Dooley <conor.dooley@microchip.com>
14 - $ref: can-controller.yaml#
18 const: microchip,mpfs-can
28 - description: AHB peripheral clock
29 - description: CAN bus clock
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/Documentation/devicetree/bindings/i2c/
Dmicrochip,corei2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip MPFS I2C Controller
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
20 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
21 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
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/Documentation/devicetree/bindings/mmc/
Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - socionext,uniphier-sd4hc
19 - const: cdns,sd4hc
36 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
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/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
Dcounters.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
13 - `Overview`_
14 - `Groups`_
15 - `Types`_
16 - `Descriptions`_
27 ----------------------------------------
29 ---------------------------------------- ---------------------------------------- |
32 | ------------------- --------------- | | ------------------- --------------- | |
34 | ------------------- --------------- | | ------------------- --------------- | |
36 | ------------------- | | ------------------- | |
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