Searched full:mpu (Results 1 – 25 of 43) sorted by relevance
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | mpu.txt | 1 * TI - MPU (Main Processor Unit) subsystem
3 The MPU subsystem contain one or several ARM cores
5 The MPU contain CPUs, GIC, L2 cache and a local PRCM.
8 - compatible : Should be "ti,omap3-mpu" for OMAP3
9 Should be "ti,omap4-mpu" for OMAP4
10 Should be "ti,omap5-mpu" for OMAP5
11 - ti,hwmods: "mpu"
27 mpu {
28 compatible = "ti,omap5-mpu";
29 ti,hwmods = "mpu"
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,omap4-wugen-mpu | 5 is also referred to as "WUGEN-MPU", hence the name of the binding.
9 - compatible : should contain at least "ti,omap4-wugen-mpu" or
10 "ti,omap5-wugen-mpu"
26 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
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| D | ti,pruss-intc.yaml | 20 including the MPU and/or other PRUSS instances, DSPs or devices.
94 connected to MPU
96 "host_intr7" interrupts connected to MPU, and other ICSSG
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| /Documentation/devicetree/bindings/sound/ |
| D | ti,omap4-mcpdm.yaml | 21 - description: MPU access base address
26 - const: mpu
64 reg = <0x0 0x7f>, /* MPU private access */
66 reg-names = "mpu", "dma";
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| D | omap-dmic.txt | 6 <MPU access base address, size>,
15 reg = <0x4012e000 0x7f>, /* MPU private access */
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| D | omap-mcbsp.txt | 9 <MPU access base address, size>,
27 reg-names = "mpu", "sidetone";
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| D | davinci-mcbsp.yaml | 29 - const: mpu
105 reg-names = "mpu", "dat";
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| D | davinci-mcasp-audio.yaml | 30 - const: mpu
188 reg-names = "mpu";
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| /Documentation/devicetree/bindings/power/ |
| D | ti-smartreflex.txt | 10 "ti,omap3-smartreflex-mpu-iva"
12 "ti,omap4-smartreflex-mpu"
43 compatible = "ti,omap4-smartreflex-mpu";
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| /Documentation/devicetree/bindings/ |
| D | resource-names.txt | 27 ranges = <0 0 0x48000000 0x00001000>, /* MPU path */
33 reg-names = "mpu", "dat",
42 reg-names = "mpu", "dma";
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| /Documentation/arch/arm/omap/ |
| D | omap_pm.rst | 34 1. Set the maximum MPU wakeup latency::
87 set_max_mpu_wakeup_lat() function to constrain the MPU wakeup
92 /* Limit MPU wakeup latency */
119 CPUFreq expresses target MPU performance levels in terms of MPU
121 specialized cases to convert that input information (OPPs/MPU
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| /Documentation/devicetree/bindings/pci/ |
| D | toshiba,visconti-pcie.yaml | 28 - description: Visconti specific memory protection unit registers (MPU)
36 - const: mpu
86 reg-names = "dbi", "config", "ulreg", "smu", "mpu";
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| /Documentation/devicetree/bindings/iio/gyroscope/ |
| D | invensense,mpu3050.yaml | 7 title: Invensense MPU-3050 Gyroscope
34 The MPU-3050 will pass through and forward the I2C signals from the
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | wkup_m3_rproc.txt | 6 that cannot be controlled from the MPU. This CM3 processor requires a firmware
14 (l4_wkup) through which it is accessible to the MPU.
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| /Documentation/devicetree/bindings/thermal/ |
| D | ti,j72xx-thermal.yaml | 84 mpu_thermal: mpu-thermal {
90 mpu_crit: mpu-crit {
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| /Documentation/arch/arm/stm32/ |
| D | stm32mp157-overview.rst | 8 The STM32MP157 is a Cortex-A MPU aimed at various applications.
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| D | stm32mp13-overview.rst | 8 The STM32MP131/STM32MP133/STM32MP135 are Cortex-A MPU aimed at various applications.
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| D | stm32mp151-overview.rst | 8 The STM32MP151 is a Cortex-A MPU aimed at various applications.
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| /Documentation/sound/ |
| D | alsa-configuration.rst | 361 port # for MPU-401 UART (0x300,0x330), -1 = disabled (default)
363 IRQ # for MPU-401 UART (3,5,7,9), -1 = disabled (default)
403 port # for MPU-401 UART (0x300,0x330), -1 = disabled (default)
405 IRQ # for MPU-401 UART (5,7,9,10), -1 = disabled (default)
544 port # for MPU-401 UART (optional), -1 = disable
548 IRQ # for MPU-401 UART
575 port # for MPU-401 UART (PnP setup - 0x300), -1 = disable
581 IRQ # for MPU-401 UART (9,11,12,15)
822 port # for MPU-401 port (0x300,0x310,0x320,0x330), -1 = disable (default)
824 IRQ # for MPU-401 port (5,7,9,10)
[all …]
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| /Documentation/arch/xtensa/ |
| D | booting.rst | 11 - For configurations without MMU, with region protection or with MPU the
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| /Documentation/devicetree/bindings/net/ |
| D | stm32-dwmac.yaml | 63 - description: For MPU family, used for power mode
64 - description: For MPU family, used for PHY without quartz
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | wkup-m3-ipc.yaml | 16 that cannot be controlled from the MPU, like suspend/resume and certain deep
61 description: wkup_m3 interrupt that signals the MPU
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| /Documentation/devicetree/bindings/regulator/ |
| D | renesas,raa215300.yaml | 14 32-bit and 64-bit MCU and MPU applications. It supports DDR3, DDR3L, DDR4,
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| /Documentation/devicetree/bindings/iio/imu/ |
| D | invensense,mpu6050.yaml | 7 title: InvenSense MPU-6050 Six-Axis (Gyro + Accelerometer) MEMS MotionTracking Device
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| /Documentation/devicetree/bindings/interconnect/ |
| D | qcom,msm8996.yaml | 61 - description: Aggregate0 NoC MPU Clock.
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