Searched +full:multi +full:- +full:channel (Results 1 – 25 of 113) sorted by relevance
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| /Documentation/devicetree/bindings/sound/ |
| D | sprd-mcdt.txt | 1 Spreadtrum Multi-Channel Data Transfer Binding
3 The Multi-channel data transfer controller is used for sound stream
5 supports 10 DAC channel and 10 ADC channel, and each channel can be
9 - compatible: Should be "sprd,sc9860-mcdt".
10 - reg: Should contain registers address and length.
11 - interrupts: Should contain one interrupt shared by all channel.
16 compatible = "sprd,sc9860-mcdt";
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| D | microchip,sama7g5-i2smcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/microchip,sama7g5-i2smcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip I2S Multi-Channel Controller
10 - Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
13 The I2SMCC complies with the Inter-IC Sound (I2S) bus specification and
15 multi-channel audio codecs. It consists of a receiver, a transmitter and a
19 multi-channel is supported by using multiple data pins, output and
23 "#sound-dai-cells":
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| D | renesas,rsnd.txt | 1 Renesas R-Car sound
7 Renesas R-Car and RZ/G sound is constructed from below modules
11 - SRC : Sampling Rate Converter
12 - CMD
13 - CTU : Channel Transfer Unit
14 - MIX : Mixer
15 - DVC : Digital Volume and Mute Function
22 * Multi channel
25 Multi channel is supported by Multi-SSI, or TDM-SSI.
27 Multi-SSI : 6ch case, you can use stereo x 3 SSI
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| /Documentation/devicetree/bindings/ |
| D | trivial-devices.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
32 - enum:
34 - acbel,fsg032
35 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
36 - ad,ad7414 # Deprecated, use adi,ad7414
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| /Documentation/sound/hd-audio/ |
| D | controls.rst | 2 HD-Audio Codec-Specific Mixer Controls
6 This file explains the codec-specific mixer controls.
9 --------------
11 Channel Mode
12 This is an enum control to change the surround-channel setup,
16 jack-retasking of multi-I/O jacks.
18 Auto-Mute Mode
19 This is an enum control to change the auto-mute behavior of the
20 headphone and line-out jacks. If built-in speakers and headphone
21 and/or line-out jacks are available on a machine, this controls
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| /Documentation/devicetree/bindings/timer/ |
| D | renesas,mtu2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Multi-Function Timer Pulse Unit 2 (MTU2)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The MTU2 is a multi-purpose, multi-channel timer/counter with configurable clock inputs
23 - enum:
24 - renesas,mtu2-r7s72100 # RZ/A1H
25 - const: renesas,mtu2
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| /Documentation/devicetree/bindings/iio/dac/ |
| D | adi,ad5696.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5696 and similar I2C multi-channel DACs
10 - Michael Auchter <michael.auchter@ni.com>
13 Binding for Analog Devices AD5696 and similar multi-channel DACs
18 - adi,ad5311r
19 - adi,ad5337r
20 - adi,ad5338r
21 - adi,ad5671r
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-qmss.txt | 5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
32 -- managed-queues : the actual queues managed by each queue manager
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| /Documentation/sound/cards/ |
| D | cmipci.rst | 2 Brief Notes on C-Media 8338/8738/8768/8770 Driver
8 Front/Rear Multi-channel Playback
9 ---------------------------------
13 DACs, both streams are handled independently unlike the 4/6ch multi-
14 channel playbacks in the section below.
22 - The first DAC supports U8 and S16LE formats, while the second DAC
24 - The second DAC supports only two channel stereo.
30 The rear output can be heard only when "Four Channel Mode" switch is
35 When "Four Channel Mode" switch is off, the output from rear speakers
43 front one) and was so excited. It was even with "Four Channel" bit
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| /Documentation/devicetree/bindings/dma/ |
| D | snps,dma-spear1340.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
21 - enum:
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| D | img-mdc-dma.txt | 1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
12 node which contains the DMA request to channel mapping registers.
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| D | stericsson,dma40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
32 10: Multi-Channel Display Engine MCDE RX
42 20: SLIMbus or HSI channel 0
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| /Documentation/fb/ |
| D | viafb.rst | 6 --------
15 ---------------
34 ----------------------
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
53 - 8, 16, 32 (default:32)
56 - 60, 75, 85, 100, 120 (default:60)
59 - 0 : expansion (default)
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| /Documentation/networking/ |
| D | multi-pf-netdev.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 Multi-PF Netdev
11 - `Background`_
12 - `Overview`_
13 - `mlx5 implementation`_
14 - `Channels distribution`_
15 - `Observability`_
16 - `Steering`_
17 - `Mutually exclusive features`_
22 The Multi-PF NIC technology enables several CPUs within a multi-socket server to connect directly to
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-lp55xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lp55xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
14 Bindings for the TI/National Semiconductor LP55xx and LP8501 multi channel
27 - national,lp5521
28 - national,lp5523
29 - ti,lp55231
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| D | leds-lp50xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lp50xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Davis <afd@ti.com>
13 The LP50XX is multi-channel, I2C RGB LED Drivers that can group RGB LEDs into
27 - ti,lp5009
28 - ti,lp5012
29 - ti,lp5018
30 - ti,lp5024
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| /Documentation/arch/mips/ |
| D | ingenic-tcu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16 64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
23 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
26 - Each TCU channel works in one of two modes:
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| /Documentation/gpu/ |
| D | mcde.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 drm/mcde ST-Ericsson MCDE Multi-channel display engine
7 .. kernel-doc:: drivers/gpu/drm/mcde/mcde_drv.c
8 :doc: ST-Ericsson MCDE Driver
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| /Documentation/driver-api/dmaengine/ |
| D | dmatest.rst | 15 The dmatest module can be configured to test a specific channel. It can also
17 competing for the same channel.
21 capability of the following: DMA_MEMCPY (memory-to-memory), DMA_MEMSET
22 (const-to-memory or memory-to-memory, when emulated), DMA_XOR, DMA_PQ.
28 Part 1 - How to build the test module
33 Device Drivers -> DMA Engine support -> DMA Test client
38 Part 2 - When dmatest is built as a module
43 % modprobe dmatest timeout=2000 iterations=1 channel=dma0chan0 run=1
50 % echo dma0chan0 > /sys/module/dmatest/parameters/channel
55 dmatest.timeout=2000 dmatest.iterations=1 dmatest.channel=dma0chan0 dmatest.run=1
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| /Documentation/devicetree/bindings/pwm/ |
| D | kontron,sl28cpld-pwm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/kontron,sl28cpld-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Walle <michael@walle.cc>
13 This module is part of the sl28cpld multi-function device. For more
16 The controller supports one PWM channel and supports only four distinct
20 - $ref: pwm.yaml#
24 const: kontron,sl28cpld-pwm
29 "#pwm-cells":
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| /Documentation/devicetree/bindings/hwmon/ |
| D | max31785.txt | 8 The Maxim MAX31785 is a PMBus device providing closed-loop, multi-channel fan
14 - compatible : One of "maxim,max31785" or "maxim,max31785a"
15 - reg : I2C address, one of 0x52, 0x53, 0x54, 0x55.
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| /Documentation/devicetree/bindings/regulator/ |
| D | renesas,raa215300.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 The RAA215300 is a high-performance, low-cost 9-channel PMIC designed for
14 32-bit and 64-bit MCU and MPU applications. It supports DDR3, DDR3L, DDR4,
16 built-in Real-Time Clock (RTC), 32kHz crystal oscillator, and coin cell
18 ideal for System-On-Module (SOM) applications. A spread spectrum feature
19 provides an ease-of-use solution for noise-sensitive audio or RF applications.
25 …-power-management/multi-channel-power-management-ics-pmics/ssdsoc-power-management-ics-pmic-and-pm…
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| /Documentation/mm/ |
| D | multigen_lru.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Multi-Gen LRU
6 The multi-gen LRU is an alternative LRU implementation that optimizes
14 ----------
20 * Simple self-correcting heuristics
23 implementations. In the multi-gen LRU, each generation represents a
25 (time-based) common frame of reference and therefore help make better
41 choices; thus self-correction is necessary.
43 The benefits of simple self-correcting heuristics are self-evident.
51 -----------
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| /Documentation/devicetree/bindings/spi/ |
| D | sprd,spi-adi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
15 ADI is the abbreviation of Anolog-Digital interface, which is used to access
24 which means we can just link one analog chip address to one hardware channel,
25 then users can access the mapped analog chip address by this hardware channel
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| /Documentation/gpu/amdgpu/display/ |
| D | dc-glossary.rst | 7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
86 Display Data Channel
108 Display Micro-Controller Unit
111 Display Micro-Controller Unit, version B
177 Multi Plane Overlay
180 Multi Stream Transport
225 Transition-Minimized Differential Signaling
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