Home
last modified time | relevance | path

Searched +full:multi +full:- +full:port (Results 1 – 25 of 104) sorted by relevance

12345

/Documentation/devicetree/bindings/net/dsa/
Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
/Documentation/devicetree/bindings/usb/
Dusb251xb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip USB 2.0 Hi-Speed Hub Controller
10 - Richard Leitner <richard.leitner@skidata.com>
15 - microchip,usb2422
16 - microchip,usb2512b
17 - microchip,usb2512bi
18 - microchip,usb2513b
19 - microchip,usb2513bi
[all …]
Dmediatek,mt6370-tcpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/mediatek,mt6370-tcpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediatTek MT6370 Type-C Port Switch and Power Delivery controller
10 - ChiYuan Huang <cy_huang@richtek.com>
13 MediaTek MT6370 is a multi-functional device.
15 regulators (DSV/VIBLDO), and TypeC Port Switch with Power Delivery controller.
16 This document only describes MT6370 Type-C Port Switch and
22 - mediatek,mt6370-tcpc
[all …]
Dmediatek,mt6360-tcpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/mediatek,mt6360-tcpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT6360 Type-C Port Switch and Power Delivery controller
10 - ChiYuan Huang <cy_huang@richtek.com>
13 Mediatek MT6360 is a multi-functional device. It integrates charger, ADC, flash, RGB indicators,
14 regulators (BUCKs/LDOs), and TypeC Port Switch with Power Delivery controller.
15 This document only describes MT6360 Type-C Port Switch and Power Delivery controller.
20 - mediatek,mt6360-tcpc
[all …]
/Documentation/arch/s390/
Dpci.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - Pierre Morel
17 -----------------------
28 ---------------
36 - /sys/kernel/debug/s390dbf/pci_msg/sprintf
56 - /sys/bus/pci/slots/XXXXXXXX/power
64 - function_id
67 - function_handle
68 Low-level identifier used for a configured PCI function.
71 - pchid
[all …]
/Documentation/netlink/specs/
Ddevlink.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 protocol: genetlink-legacy
10 -
12 name: sb-pool-type
14 -
16 -
18 -
20 name: port-type
22 -
24 -
[all …]
/Documentation/networking/device_drivers/ethernet/ti/
Dam65_nuss_cpsw_switchdev.rst1 .. SPDX-License-Identifier: GPL-2.0
9 Port renaming
14 ip -d link show dev sw0p1 | grep switchid
20 Multi mac mode
23 - The driver is operating in multi-mac mode by default, thus
29 See Documentation/networking/devlink/am65-nuss-cpsw-switch.rst
40 This can be done regardless of the state of Port's netdev devices - UP/DOWN, but
41 Port's netdev devices have to be in UP before joining to the bridge to avoid
43 configuration when first port changes its state to UP.
45 When the both interfaces joined the bridge - CPSW switch driver will enable
[all …]
/Documentation/devicetree/bindings/sound/
Dnvidia,tegra210-mvc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-mvc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 signal path. It can be used in input or output signal path for per-stream
14 multi-channel (up to 7.1 channels) stream. An independent mute control is
18 - Jon Hunter <jonathanh@nvidia.com>
19 - Mohan Kumar <mkumard@nvidia.com>
20 - Sameer Pujar <spujar@nvidia.com>
23 - $ref: dai-common.yaml#
[all …]
Dnvidia,tegra210-ope.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ope.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 PEQ (Parametric Equalizer) and MBDRC (Multi Band Dynamic Range Compressor)
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Mohan Kumar <mkumard@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
20 - $ref: dai-common.yaml#
25 - const: nvidia,tegra210-ope
[all …]
Dti,pcm3168a.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Horsley <Damien.Horsley@imgtec.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
12 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 The Texas Instruments PCM3168A is a 24-bit Multi-channel Audio CODEC with
27 - description: System clock input
29 clock-names:
31 - const: scki
[all …]
/Documentation/admin-guide/perf/
Dhisi-pcie-pmu.rst8 Each PCIe Core has a PMU to monitor multi Root Ports of this PCIe Core and
15 The PCIe PMU driver registers a perf PMU with the name of its sicl-id and PCIe
40 ------------------------------------------
42 $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=0xffff/
43 $# perf stat -e hisi_pcie0_core0/rx_mwr_cnt,port=0xffff/
56 …$# perf stat -e "{hisi_pcie0_core0/rx_mwr_latency,port=0xffff/,hisi_pcie0_core0/rx_mwr_cnt,port=0x…
62 --------------
67 Ports or downstream target Endpoint. PCIe PMU driver support "port" and
71 "port" filter is valid.
72 If "port" filter not being set or is set explicitly to zero (default), the
[all …]
/Documentation/devicetree/bindings/net/
Dethernet-switch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vladimir Oltean <olteanv@gmail.com>
15 Ethernet switches are multi-port Ethernet controllers. Each port has
25 # nodes have to preserve non-standard names because of
26 # backward-compatibility with boot loaders inspecting certain
[all …]
Dmicrochip,lan966x-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
[all …]
Dethernet-phy-package.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy-package.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
13 PHY packages are multi-port Ethernet PHY of the same family
23 pattern: "^ethernet-phy-package@[a-f0-9]+$"
37 '#address-cells':
40 '#size-cells':
44 ^ethernet-phy@[a-f0-9]+$:
[all …]
/Documentation/devicetree/bindings/arm/
Dqcom,coresight-tpdm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/qcom,coresight-tpdm.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Trace, Profiling and Diagnostics Monitor - TPDM
13 Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
22 - Mao Jinlong <quic_jinlmao@quicinc.com>
23 - Tao Zhang <quic_taozha@quicinc.com>
31 - qcom,coresight-tpdm
33 - compatible
[all …]
/Documentation/devicetree/bindings/media/i2c/
Dtechwell,tw9900.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mehdi Djait <mehdi.djait@bootlin.com>
13 The tw9900 is a multi-standard video decoder, supporting NTSC, PAL standards
14 with auto-detection features.
23 vdd-supply:
26 reset-gpios:
30 powerdown-gpios:
38 port@0:
[all …]
/Documentation/firmware-guide/acpi/apei/
Doutput_format.rst1 .. SPDX-License-Identifier: GPL-2.0
55 [cache error][, TLB error][, bus error][, micro-architectural error]
81 unknown | no error | single-bit ECC | multi-bit ECC | \
82 single-symbol chipkill ECC | multi-symbol chipkill ECC | master abort | \
88 [port_type: <integer>, <pcie port type string>]
104 <pcie port type string>* := PCIe end point | legacy PCI end point | \
105 unknown | unknown | root port | upstream switch port | \
106 downstream switch port | PCIe to PCI/PCI-X bridge | \
107 PCI/PCI-X to PCIe bridge | root complex integrated endpoint device | \
121 Replay Timer Timeout | Advisory Non-Fatal
/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
108 Display Micro-Controller Unit
111 Display Micro-Controller Unit, version B
177 Multi Plane Overlay
180 Multi Stream Transport
216 Scalable Data Port
225 Transition-Minimized Differential Signaling
/Documentation/trace/
Dintel_th.rst1 .. SPDX-License-Identifier: GPL-2.0
8 --------
23 - Software Trace Hub (STH), trace source, which is a System Trace
25 - Memory Storage Unit (MSU), trace output, which allows storing
27 - Parallel Trace Interface output (PTI), trace output to an external
28 debug host via a PTI port,
29 - Global Trace Hub (GTH), which is a switch and a central component
33 Documentation/ABI/testing/sysfs-bus-intel_th-output-devices, the most
39 description is at Documentation/ABI/testing/sysfs-bus-intel_th-devices-gth.
54 [1] https://software.intel.com/sites/default/files/managed/d3/3c/intel-th-developer-manual.pdf
[all …]
/Documentation/devicetree/bindings/ata/
Dfaraday,ftide010.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
15 platform. The controller can do PIO modes 0 through 4, Multi-word DMA
22 The timing properties are unique per-SoC, not per-board.
27 - const: faraday,ftide010
28 - items:
29 - const: cortina,gemini-pata
30 - const: faraday,ftide010
[all …]
/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
Dcounters.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
13 - `Overview`_
14 - `Groups`_
15 - `Types`_
16 - `Descriptions`_
27 ----------------------------------------
29 ---------------------------------------- ---------------------------------------- |
32 | ------------------- --------------- | | ------------------- --------------- | |
34 | ------------------- --------------- | | ------------------- --------------- | |
36 | ------------------- | | ------------------- | |
[all …]
Dkconfig.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
34 | built-in into mlx5_core.ko.
39 …g (DCB) Support <https://enterprise-support.nvidia.com/s/article/howto-auto-config-pfc-and-ets-on-…
53 | Flow-based classifiers, such as those registered through
54 | `tc-flower(8)`, are processed by the device, rather than the
61 | Enables Hardware-accelerated receive flow steering (arfs) support, and ntuple filtering.
62 | https://enterprise-support.nvidia.com/s/article/howto-configure-arfs-on-connectx-4
67 | Enables :ref:`IPSec XFRM cryptography-offload acceleration <xfrm_device>`.
72 | Build support for MACsec cryptography-offload acceleration in the NIC.
83 | TLS cryptography-offload acceleration.
[all …]
/Documentation/devicetree/bindings/dma/
Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
26 4: I2C port 1
27 5: I2C port 3
28 6: I2C port 2
[all …]
/Documentation/sound/cards/
Dcmipci.rst2 Brief Notes on C-Media 8338/8738/8768/8770 Driver
8 Front/Rear Multi-channel Playback
9 ---------------------------------
13 DACs, both streams are handled independently unlike the 4/6ch multi-
22 - The first DAC supports U8 and S16LE formats, while the second DAC
24 - The second DAC supports only two channel stereo.
51 control switch in the driver "Line-In As Rear", which you can change
52 via alsamixer or somewhat else. When this switch is on, line-in jack
60 4/6 Multi-Channel Playback
61 --------------------------
[all …]
/Documentation/networking/
Drepresentors.rst1 .. SPDX-License-Identifier: GPL-2.0
9 used to control internal switching on SmartNICs. For the closely-related port
10 representors on physical (multi-port) switches, see
14 ----------
16 Since the mid-2010s, network cards have started offering more complex
17 virtualisation capabilities than the legacy SR-IOV approach (with its simple
18 MAC/VLAN-based switching model) can support. This led to a desire to offload
19 software-defined networks (such as OpenVSwitch) to these NICs to specify the
24 virtual switches and IOV devices. Just as each physical port of a Linux-
25 controlled switch has a separate netdev, so does each virtual port of a virtual
[all …]

12345