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/Documentation/devicetree/bindings/hwinfo/
Dti,k3-socinfo.yaml7 title: Texas Instruments K3 Multicore SoC platforms chipid module
14 Texas Instruments (ARM64) K3 Multicore SoC platforms chipid module is
/Documentation/devicetree/bindings/perf/
Darm,dsu-pmu.yaml16 L3 memory system, control logic and external interfaces to form a multicore
/Documentation/admin-guide/perf/
Darm_dsu_pmu.rst6 control logic and external interfaces to form a multicore cluster. The PMU
/Documentation/devicetree/bindings/sound/
Dxmos,xvf3500.yaml14 multicore controller for voice processing.
/Documentation/devicetree/bindings/powerpc/fsl/
Dccf.txt6 that enables the implementation of coherent, multicore systems.
/Documentation/devicetree/bindings/arm/ti/
Dk3.yaml7 title: Texas Instruments K3 Multicore SoC architecture
13 Platforms based on Texas Instruments K3 Multicore SoC architecture
/Documentation/devicetree/bindings/arm/
Darm,realview.yaml15 earlier CPUs such as TrustZone and multicore (MPCore).
Darm,vexpress-juno.yaml15 multicore Cortex-A class systems. The Versatile Express family contains both
/Documentation/devicetree/bindings/
Dtrivial-devices.yaml92 # DA9053: flexible system level PMIC with multicore support
/Documentation/admin-guide/pm/
Dcpufreq.rst124 multicore processor, or a hardware thread in a physical processor or processor
605 cores in a multicore package temporarily (and above the sustainable frequency
Dintel_pstate.rst243 multicore processor to opportunistically increase the P-state of one or more
/Documentation/scheduler/
Dsched-deadline.rst540 17 - L. Abeni, G. Lipari, A. Parri, Y. Sun, Multicore CPU reclaiming: parallel
/Documentation/RCU/
DRTFP.txt2323 ,Title="Deterministic Synchronization in Multicore Systems: the Role of {RCU}"
/Documentation/RCU/Design/Requirements/
DRequirements.rst1493 part due to the collision of multicore hardware with object-oriented