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/Documentation/devicetree/bindings/mux/
Dmux-consumer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-consumer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
13 Mux controller consumers should specify a list of mux controllers that they
14 want to use with a property containing a 'mux-ctrl-list':
16 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
17 single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
18 mux-ctrl-phandle : phandle to mux controller node
[all …]
Dmux-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
13 A multiplexer (or mux) controller will have one, or several, consumer devices
14 that uses the mux controller. Thus, a mux controller can possibly control
16 multiplexer needed by each consumer, but a single mux controller can of course
17 control several multiplexers for a single consumer.
19 A mux controller provides a number of states to its consumers, and the state
[all …]
Dadi,adg792a.txt4 - compatible : "adi,adg792a" or "adi,adg792g"
5 - #mux-control-cells : <0> if parallel (the three muxes are bound together
6 with a single mux controller controlling all three muxes), or <1> if
7 not (one mux controller for each mux).
8 * Standard mux-controller bindings as described in mux-controller.yaml
11 - gpio-controller : if present, #gpio-cells below is required.
12 - #gpio-cells : should be <2>
13 - First cell is the GPO line number, i.e. 0 or 1
14 - Second cell is used to specify active high (0)
18 - idle-state : if present, array of states that the mux controllers will have
[all …]
Dgpio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/gpio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
13 Define what GPIO pins are used to control a multiplexer. Or several
14 multiplexers, if the same pins control more than one multiplexer.
22 const: gpio-mux
24 mux-gpios:
[all …]
Dadi,adgs1408.txt1 Bindings for Analog Devices ADGS1408/1409 8:1/Dual 4:1 Mux
4 - compatible : Should be one of
7 * Standard mux-controller bindings as described in mux-controller.yaml
10 - gpio-controller : if present, #gpio-cells is required.
11 - #gpio-cells : should be <2>
12 - First cell is the GPO line number, i.e. 0 to 3
14 - Second cell is used to specify active high (0)
18 - idle-state : if present, the state that the mux controller will have
28 * One mux controller.
29 * Mux state set to idle as is (no idle-state declared)
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/Documentation/devicetree/bindings/iio/multiplexer/
Dio-channel-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/multiplexer/io-channel-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
16 For each non-empty string in the channels property, an io-channel will be
17 created. The number of this io-channel is the same as the index into the list
18 of strings in the channels property, and also matches the mux controller
19 state. The mux controller state is described in
20 Documentation/devicetree/bindings/mux/mux-controller.yaml
[all …]
/Documentation/devicetree/bindings/clock/
Dkeystone-pll.txt9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
23 #clock-cells = <0>;
24 compatible = "ti,keystone,main-pll-clock";
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Dimx6ul-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx6ul-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abel Vesa <abelvesa@kernel.org>
11 - Peng Fan <peng.fan@nxp.com>
15 const: fsl,imx6ul-ccm
22 interrupt for frequency or mux change, request 2 is to generate
25 - description: CCM interrupt request 1
26 - description: CCM interrupt request 2
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Dimx6sll-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx6sll-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abel Vesa <abelvesa@kernel.org>
11 - Peng Fan <peng.fan@nxp.com>
15 const: fsl,imx6sll-ccm
22 interrupt for frequency or mux change, request 2 is to generate
25 - description: CCM interrupt request 1
26 - description: CCM interrupt request 2
[all …]
Dimx6sx-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx6sx-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abel Vesa <abelvesa@kernel.org>
11 - Peng Fan <peng.fan@nxp.com>
15 const: fsl,imx6sx-ccm
22 interrupt for frequency or mux change, request 2 is to generate
25 - description: CCM interrupt request 1
26 - description: CCM interrupt request 2
[all …]
/Documentation/devicetree/bindings/usb/
Dchipidea,usb2-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
25 clock-names:
31 power-domains:
37 reset-names:
40 "#reset-cells":
45 itc-setting:
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Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nuvoton,npcm750-udc
[all …]
/Documentation/devicetree/bindings/sound/
Dsamsung-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - $ref: dai-common.yaml#
19 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
21 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
22 secondary FIFO, s/w reset control and internal mux for root clock
[all …]
Dmt2701-cs42448.txt4 - compatible: "mediatek,mt2701-cs42448-machine"
5 - mediatek,platform: the phandle of MT2701 ASoC platform
6 - audio-routing: a list of the connections between audio
7 - mediatek,audio-codec: the phandles of cs42448 codec
8 - mediatek,audio-codec-bt-mrg the phandles of bt-sco dummy codec
9 - pinctrl-names: Should contain only one value - "default"
10 - pinctrl-0: Should specify pin control groups used for this controller.
11 - i2s1-in-sel-gpio1, i2s1-in-sel-gpio2: Should specify two gpio pins to
12 control I2S1-in mux.
17 compatible = "mediatek,mt2701-cs42448-machine";
[all …]
/Documentation/devicetree/bindings/clock/ti/
Dmux.txt1 Binding for TI mux clock.
4 register-mapped multiplexer with multiple input clock signals or
22 "index-starts-at-one" modified the scheme as follows:
29 The binding must provide the register to control the mux. Optionally
30 the number of bits to shift the control field in the register can be
34 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
37 - compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
38 - #clock-cells : from common clock binding; shall be set to 0.
39 - clocks : link phandles of parent clocks
40 - reg : register offset for register controlling adjustable mux
[all …]
/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dcortina,gemini-pinctrl.txt4 see further arm/gemini.txt. It is a purely group-based multiplexing pin
10 - compatible: "cortina,gemini-pinctrl"
12 Subnodes of the pin controller contain pin control multiplexing set-up
15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
19 - skew-delay is supported on the Ethernet pins
20 - drive-strength with 4, 8, 12 or 16 mA as argument is supported for
28 compatible = "cortina,gemini-syscon";
31 compatible = "cortina,gemini-pinctrl";
32 pinctrl-names = "default";
33 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
[all …]
Dsunplus,sp7021-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
23 (1) function-group pins:
24 Ex 1 (SPI-NOR flash):
[all …]
Dberlin,pinctrl.txt1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
21 "marvell,berlin2cd-system-pinctrl",
[all …]
Dpinctrl-sirf.txt4 - compatible : "sirf,prima2-pinctrl"
5 - reg : Address range of the pinctrl registers
6 - interrupts : Interrupts used by every GPIO group
7 - gpio-controller : Indicates this device is a GPIO controller
8 - interrupt-controller : Marks the device node as an interrupt controller
10 - sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
11 - sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m
13 Please refer to pinctrl-bindings.txt in this directory for details of the common
19 Required subnode-properties:
20 - sirf,pins : An array of strings. Each string contains the name of a group.
[all …]
/Documentation/devicetree/bindings/fsi/
Daspeed,ast2600-fsi-master.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eddie James <eajames@linux.ibm.com>
19 - aspeed,ast2600-fsi-master
20 - aspeed,ast2700-fsi-master
25 cfam-reset-gpios:
30 fsi-routing-gpios:
33 Output GPIO pin for setting the FSI mux (internal or cabled)
[all …]
/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
[all …]
/Documentation/devicetree/bindings/display/imx/
Dldb.txt1 Device-Tree bindings for LVDS Display Bridge (ldb)
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
18 control register.
19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
21 Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
/Documentation/devicetree/bindings/net/
Dti,k3-am654-cpts.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpts.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Siddharth Vadapalli <s-vadapalli@ti.com>
11 - Roger Quadros <rogerq@kernel.org>
14 The TI AM654x/J721E CPTS module is used to facilitate host control of time
17 - selection of multiple external clock sources
18 - Software control of time sync events via interrupt or polling
19 - 64-bit timestamp mode in ns with PPM and nudge adjustment.
[all …]
/Documentation/devicetree/bindings/spi/
Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
[all …]

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