Searched +full:mux +full:- +full:locked (Results 1 – 5 of 5) sorted by relevance
6 than a straight-forward I2C bus with one adapter and one or more devices.10 1. A mux may be needed on the bus to prevent address collisions.25 I2C transfers, and all adapters with a parent are part of an "i2c-mux"28 Depending of the particular mux driver, something happens when there is29 an I2C transfer on one of its child adapters. The mux driver can30 obviously operate a mux, but it can also do arbitration with an external31 bus master or open a gate. The mux driver has two operations for this,40 mux-locked or parent-locked muxes.43 Mux-locked muxes44 ----------------[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: General Purpose I2C Bus Mux10 - Peter Rosin <peda@axentia.se>13 This binding describes an I2C bus multiplexer that uses a mux controller14 from the mux subsystem to route the I2C signals.16 .-----. .-----.18 .------------. '-----' '-----'[all …]
1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)8 -16 -20 -23 render-max: true24 -26 name: lock-status31 -34 dpll was not yet locked to any valid input (or forced by setting37 -[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Frank Li <Frank.Li@nxp.com>15 multiple phase locked loops (PLL) to create a variety of frequencies24 --------------- -------------36 - items:37 - enum:38 - fsl,p2041-clockgen[all …]
1 .. SPDX-License-Identifier: GPL-2.010 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock14 DPLL - Digital Phase Locked Loop is an integrated circuit which in82 - ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device83 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll89 - ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid91 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as104 1) Set on a pin - the configuration affects all dpll devices pin is106 2) Set on a pin-dpll tuple - the configuration affects only selected110 MUX-type pins[all …]