Searched full:mv (Results 1 – 25 of 110) sorted by relevance
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| /Documentation/hwmon/ |
| D | ina209.rst | 40 in0_input shunt voltage (mV)
41 in0_input_highest shunt voltage historical maximum reading (mV)
42 in0_input_lowest shunt voltage historical minimum reading (mV)
44 in0_max shunt voltage max alarm limit (mV)
45 in0_min shunt voltage min alarm limit (mV)
46 in0_crit_max shunt voltage crit max alarm limit (mV)
47 in0_crit_min shunt voltage crit min alarm limit (mV)
53 in1_input bus voltage (mV)
54 in1_input_highest bus voltage historical maximum reading (mV)
55 in1_input_lowest bus voltage historical minimum reading (mV)
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| D | ina238.rst | 35 in0_input Shunt voltage (mV)
36 in0_min Minimum shunt voltage threshold (mV)
38 in0_max Maximum shunt voltage threshold (mV)
41 in1_input Bus voltage (mV)
42 in1_min Minimum bus voltage threshold (mV)
44 in1_max Maximum bus voltage threshold (mV)
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| D | ltc4245.rst | 52 in1_input 12v input voltage (mV)
53 in2_input 5v input voltage (mV)
54 in3_input 3v input voltage (mV)
55 in4_input Vee (-12v) input voltage (mV)
72 in5_input 12v output voltage (mV)
73 in6_input 5v output voltage (mV)
74 in7_input 3v output voltage (mV)
75 in8_input Vee (-12v) output voltage (mV)
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| D | xdpe12284.rst | 41 - VR12.0 mode, 5-mV DAC - 0x01.
42 - VR12.5 mode, 10-mV DAC - 0x02.
43 - IMVP9 mode, 5-mV DAC - 0x03.
44 - AMD mode 6.25mV - 0x10.
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| D | max127.rst | 33 in[0-7]_input The input voltage (in mV) of the corresponding channel.
36 in[0-7]_min The lower input limit (in mV) for the corresponding channel.
41 in[0-7]_max The higher input limit (in mV) for the corresponding channel.
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| D | w83793.rst | 48 voltage0-2 is 2mV, resolution of voltage3/4/5 is 16mV, 8mV for voltage6,
49 24mV for voltage7/8. Temp1-4 have a 0.25 degree Celsius resolution,
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| D | stpddc60.rst | 38 output voltage as a positive or negative offset in the interval 50mV to 400mV
39 in 50mV steps. This means that the absolute values of the limits will change
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| D | ltc4151.rst | 50 in1_input VDIN voltage (mV)
52 in2_input ADIN voltage (mV)
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| D | vt1211.rst | 82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
98 +2.5V 2K 10K 1.2 2083 mV
99 VccP --- --- 1.0 1400 mV [1]_
100 +5V 14K 10K 2.4 2083 mV
101 +12V 47K 10K 5.7 2105 mV
102 +3.3V (int) 2K 3.4K 1.588 3300 mV [2]_
103 +3.3V (ext) 6.8K 10K 1.68 1964 mV
157 Vpin = 2200 * Rth / (Rs + Rth) (2200 is the ADC max limit of 2200 mV)
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| /Documentation/devicetree/bindings/sound/ |
| D | cs35l33.txt | 22 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
23 a value of 1 and will increase at a step size of 100mV until a maximum of
24 8000mV.
62 stage enters LDO operation. Starts as a default value of 50mV for a value
63 of 1 and increases with a step size of 50mV to a maximum of 750mV (value of
80 The reference voltage starts at 3000mV with a value of 0x3 and is increased
81 by 100mV per step to a maximum of 5500mV.
91 1800mV with a step size of 50mV up to a maximum value of 1750mV.
92 Default is 1800mV.
109 cirrus,boost-ctl = <0x30>; /* VBST = 8000mV */
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| D | cs35l36.txt | 14 converter's output voltage in mV. The range is from 2550mV to 12000mV with
15 increments of 50mV.
75 weak-FET operation. The range is 50mV to 700mV in 50mV increments.
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| /Documentation/devicetree/bindings/regulator/ |
| D | tps51632-regulator.txt | 9 - ti,dvfs-step-20mV: The 20mV step voltage when PWM DVFS enabled. Missing this
10 will set 10mV step voltage in PWM DVFS mode. In normal mode, the voltage
11 step is 10mV as per datasheet.
26 ti,dvfs-step-20mV;
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| D | maxim,max8952.yaml | 46 - 0: 32mV/us
47 - 1: 16mV/us
48 - 2: 8mV/us
49 - 3: 4mV/us
50 - 4: 2mV/us
51 - 5: 1mV/us
52 - 6: 0.5mV/us
53 - 7: 0.25mV/us
54 Defaults to 32mV/us if not specified.
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| D | richtek,rt6160-regulator.yaml | 14 up to 3A output current from 2025mV to 5200mV. And it support the wide
15 input voltage range from 2200mV to 5500mV.
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| D | nvidia,tegra-regulators-coupling.txt | 12 The CORE and RTC voltages shall be in a range of 170mV from each other
13 and they both shall be higher than the CPU voltage by at least 120mV.
19 and CPU voltages shall be in a range of 300mV from each other and CORE
20 voltage shall be higher than the CPU by N mV, where N depends on the CPU
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| D | mediatek,mt6358-regulator.yaml | 79 description: LDOs with fixed 1.2V output and 0~100/10mV tuning
88 LDOs with fixed 1.8V output and 0~100/10mV tuning (vcn18 on MT6366 has variable output)
96 description: LDOs with fixed 2.2V output and 0~100/10mV tuning
104 description: LDOs with fixed 2.8V output and 0~100/10mV tuning
112 description: LDOs with fixed 3.0V output and 0~100/10mV tuning
128 description: LDOs with variable output and 0~100/10mV tuning
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| D | ltc3676.txt | 21 412.5mV to 800mV in 12.5 mV steps. The output voltage thus ranges between
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| D | rohm,bd96801-regulator.yaml | 33 Initial voltage for regulator. Voltage can be tuned +/-150 mV from
50 Initial voltage for regulator. Voltage can be tuned +/-150 mV from
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| D | richtek,rt5739.yaml | 14 programmable output voltage from 300mV to 1300mV with wide input voltage
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| /Documentation/devicetree/bindings/input/ |
| D | ti,drv260x.yaml | 67 vib-rated-mv:
71 If this is not set then the value will be defaulted to 3200 mV.
74 vib-overdrive-mv:
78 If this is not set then the value will be defaulted to 3200 mV.
106 vib-rated-mv = <3200>;
107 vib-overdrive-mv = <3200>;
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| /Documentation/devicetree/bindings/mmc/ |
| D | mmc-spi-slot.yaml | 32 Two cells are required, first cell specifies minimum slot voltage (mV),
33 second cell specifies maximum slot voltage (mV).
37 value for minimum slot voltage in mV
40 value for maximum slot voltage in mV
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-stm32-usbphyc.yaml | 110 - <1> increases the level by 5 to 7 mV
111 - <2> increases the level by 10 to 14 mV
112 - <3> decreases the level by 5 to 7 mV
166 - <1> = threshold shift by +7 mV
167 - <2> = threshold shift by -5 mV
168 - <3> = threshold shift by +14 mV
182 - <1> = offset of +5 mV
183 - <2> = offset of +10 mV
184 - <3> = offset of -5 mV
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| /Documentation/devicetree/bindings/net/ |
| D | mscc-phy-vsc8531.txt | 4 - vsc8531,vddmac : The vddmac in mV. Allowed values is listed
42 | 3300 mV 2500 mV 1800 mV 1500 mV |
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| /Documentation/power/regulator/ |
| D | overview.rst | 100 - voltage output is in the range 800mV -> 3500mV.
108 - Domain-1 voltage is 3300mV
109 - Domain-2 voltage is 1400mV -> 1600mV
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| /Documentation/devicetree/bindings/mfd/ |
| D | ti,tps65086.yaml | 60 ti,regulator-step-size-25mv:
63 Set this if the regulator is factory set with a 25mv step voltage
119 ti,regulator-step-size-25mv;
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