| /Documentation/devicetree/bindings/mtd/ |
| D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
5 - "nvidia,tegra20-nand"
11 - nand
15 - nand
18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported.
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
29 - nand-bus-width : See nand-controller.yaml
30 - nand-on-flash-bbt: See nand-controller.yaml
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| D | marvell,nand-controller.yaml | 4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
7 title: Marvell NAND Flash Controller (NFC)
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
19 - marvell,ac5-nand-controller
20 - marvell,armada370-nand-controller
21 - marvell,pxa3xx-nand-controller
25 - marvell,armada-8k-nand
26 - marvell,armada370-nand
27 - marvell,pxa3xx-nand
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| D | brcm,brcmnand.yaml | 7 title: Broadcom STB NAND Controller
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
27 -- Additional SoC-specific NAND controller properties --
29 The NAND controller is integrated differently on the variety of SoCs on which
31 bits with which to control the 8 exposed NAND interrupts, as well as hardware
35 interesting ways, sometimes with registers that lump multiple NAND-related
39 register resources within the NAND controller node above.
58 - description: BCMBCA SoC-specific NAND controller
60 - const: brcm,nand-bcm63138
65 - description: iProc SoC-specific NAND controller
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| D | denali,nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/denali,nand.yaml#
7 title: Denali NAND controller
15 - altr,socfpga-denali-nand
16 - socionext,uniphier-denali-nand-v5a
17 - socionext,uniphier-denali-nand-v5b
38 nand: controller core clock
42 - const: nand
53 nand: controller core reset
57 - const: nand
59 - const: nand
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| D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
10 - #address-cells: shall be set to 1. Encode the nand CS.
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
15 in a board stuffing. Typical NAND memory timings derived from this
23 Children nodes represent the available nand chips. Currently the driver can
24 only handle one NAND chip.
28 - nand-bus-width: see nand-controller.yaml
29 - nand-ecc-mode: see nand-controller.yaml
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| D | samsung-s3c2410.txt | 1 * Samsung S3C2410 and compatible NAND flash controller
5 "samsung,s3c2410-nand"
6 "samsung,s3c2412-nand"
7 "samsung,s3c2440-nand"
9 - #address-cells, #size-cells : see nand-controller.yaml
10 - clocks : phandle to the nand controller clock
11 - clock-names : must contain "nand"
14 Child nodes representing the available nand chips.
17 - nand-ecc-mode : see nand-controller.yaml
18 - nand-on-flash-bbt : see nand-controller.yaml
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| D | qcom,nandc.yaml | 7 title: Qualcomm NAND controller
15 - qcom,ipq806x-nand
16 - qcom,ipq4019-nand
17 - qcom,ipq6018-nand
18 - qcom,ipq8074-nand
19 - qcom,sdx55-nand
38 the NAND controller on the given platform
44 the NAND controller on the given platform
47 "^nand@[a-f0-9]$":
49 $ref: raw-nand-chip.yaml
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| D | hisi504-nand.txt | 1 Hisilicon Hip04 Soc NAND controller DT binding
7 NAND controller's registers. The second contains base
8 physical address and size of NAND controller's buffer.
10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
29 nand: nand@4020000 {
33 nand-bus-width = <8>;
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| D | atmel-nand.txt | 1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
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| D | fsmc-nand.txt | 2 NAND Interface
5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
33 - nand-ecc-mode : see nand-controller.yaml
34 - nand-ecc-strength : see nand-controller.yaml
35 - nand-ecc-step-size : see nand-controller.yaml
43 compatible = "st,spear600-fsmc-nand";
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| D | gpmi-nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
13 The GPMI nand controller provides an interface to control the NAND
22 - fsl,imx23-gpmi-nand
23 - fsl,imx28-gpmi-nand
24 - fsl,imx6q-gpmi-nand
25 - fsl,imx6sx-gpmi-nand
26 - fsl,imx7d-gpmi-nand
27 - fsl,imx8qxp-gpmi-nand
30 - fsl,imx8mm-gpmi-nand
31 - fsl,imx8mn-gpmi-nand
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| D | davinci-nand.txt | 1 Device tree bindings for Texas instruments Davinci/Keystone NAND controller
4 NAND interface contains.
12 - compatible: "ti,davinci-nand"
13 "ti,keystone-nand"
22 for accessing the nand.
29 address for the chip select space the NAND Flash
35 address for the chip select space the NAND Flash
42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
50 - nand-bus-width: buswidth 8 or 16. If not present 8.
52 - nand-on-flash-bbt: use flash based bad block table support. OOB
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| D | technologic,nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/technologic,nand.yaml#
7 title: Technologic Systems NAND controller
13 - $ref: nand-controller.yaml
18 - const: technologic,ts7200-nand
21 - technologic,ts7300-nand
22 - technologic,ts7260-nand
23 - technologic,ts7250-nand
24 - const: technologic,ts7200-nand
37 nand-controller@60000000 {
38 compatible = "technologic,ts7200-nand";
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| D | nand-controller.yaml | 4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
7 title: NAND Controller Common Properties
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
21 pattern: "^nand-controller(@.*)?"
35 NAND controller (even if they are not used). As many additional
37 lines. 'reg' entries of the NAND chip subnodes become indexes of
43 "^nand@[a-f0-9]$":
45 $ref: raw-nand-chip.yaml#
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| D | amlogic,meson-nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml#
7 title: Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
10 - $ref: nand-controller.yaml
41 "^nand@[0-7]$":
43 $ref: raw-nand-chip.yaml
49 nand-ecc-mode:
52 nand-ecc-step-size:
55 nand-ecc-strength:
62 nand-rb:
86 nand-ecc-strength: [nand-ecc-step-size]
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| D | ti,gpmc-nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
7 title: Texas Instruments GPMC NAND Flash controller.
14 GPMC NAND controller/Flash is represented as a child of the
21 - ti,am64-nand
22 - ti,omap2-nand
36 ti,nand-ecc-opt:
41 ti,nand-xfer-type:
52 nand-bus-width:
54 Bus width to the NAND chip
61 GPIO connection to R/B signal from NAND chip
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| D | ingenic,nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml#
7 title: Ingenic SoCs NAND controller
13 - $ref: nand-controller.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
21 - ingenic,jz4780-nand
25 - description: Bank number, offset and size of first attached NAND chip
26 - description: Bank number, offset and size of second attached NAND chip
27 - description: Bank number, offset and size of third attached NAND chip
28 - description: Bank number, offset and size of fourth attached NAND chip
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| D | mediatek,mtk-nfc.yaml | 7 title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC)
42 "^nand@[a-f0-9]$":
43 $ref: raw-nand-chip.yaml#
48 nand-ecc-mode:
52 - $ref: nand-controller.yaml#
61 "^nand@[a-f0-9]$":
63 nand-ecc-step-size:
65 nand-ecc-strength:
76 "^nand@[a-f0-9]$":
78 nand-ecc-step-size:
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| D | mxic-nand.txt | 1 Macronix Raw NAND Controller Device Tree Bindings
5 - compatible: should be "mxic,multi-itfc-v009-nand-controller"
9 - interrupts: interrupt line connected to this raw NAND controller
15 - children nodes represent the available NAND chips.
17 See Documentation/devicetree/bindings/mtd/nand-controller.yaml
22 nand: nand-controller@43c30000 {
23 compatible = "mxic,multi-itfc-v009-nand-controller";
31 nand@0 {
33 nand-ecc-mode = "soft";
34 nand-ecc-algo = "bch";
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| D | nand-chip.yaml | 4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
7 title: NAND Chip Common Properties
16 This file covers the generic description of a NAND chip. It implies that the
17 bus interface should not be taken into account: both raw NAND devices and
18 SPI-NAND devices are concerned by this description.
25 nand-ecc-engine:
29 1/ The ECC engine is part of the NAND controller, in this
31 2/ The ECC engine is part of the NAND part (on-die), in this
37 nand-use-soft-ecc-engine:
41 nand-no-ecc-engine:
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| D | rockchip,nand-controller.yaml | 4 $id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
7 title: Rockchip SoCs NAND FLASH Controller (NFC)
10 - $ref: nand-controller.yaml#
58 "^nand@[0-7]$":
60 $ref: raw-nand-chip.yaml
66 nand-ecc-mode:
69 nand-ecc-step-size:
72 nand-ecc-strength:
88 nand-bus-width:
98 Only used in combination with 'nand-is-boot-medium'.
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| D | cadence-nand-controller.txt | 1 * Cadence NAND controller
16 - dmas: shall reference DMA channel associated to the NAND controller
24 Child nodes represent the available NAND chips.
26 Required properties of NAND chips:
28 the cadence nand flash controller
30 See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
35 nand_controller: nand-controller@60000000 {
44 nand@0 {
46 label = "nand-1";
48 nand@1 {
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| D | raw-nand-chip.yaml | 4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
7 title: Raw NAND Chip Common Properties
13 - $ref: nand-chip.yaml#
19 {size} bytes for a particular raw NAND chip.
28 pattern: "^nand@[a-f0-9]$"
34 nand-ecc-placement:
44 nand-ecc-mode:
52 nand-bus-width:
54 Bus width to the NAND chip
59 nand-on-flash-bbt:
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| D | allwinner,sun4i-a10-nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
7 title: Allwinner A10 NAND Controller
10 - $ref: nand-controller.yaml
19 - allwinner,sun4i-a10-nand
20 - allwinner,sun8i-a23-nand-controller
50 "^nand@[a-f0-9]$":
52 $ref: raw-nand-chip.yaml
58 nand-ecc-algo:
61 nand-ecc-step-size:
64 nand-ecc-strength:
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | lantiq,pinctrl-xway.txt | 56 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
67 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
79 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
93 exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
94 nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
95 nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
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