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| /Documentation/hwmon/ |
| D | mc13783-adc.rst | 1 Kernel driver mc13783-adc
10 Datasheet: https://www.nxp.com/docs/en/data-sheet/MC13783.pdf
16 Datasheet: https://www.nxp.com/docs/en/data-sheet/MC13892.pdf
22 - Sascha Hauer <s.hauer@pengutronix.de>
23 - Luotao Fu <l.fu@pengutronix.de>
26 -----------
29 Among other things they contain a 10-bit A/D converter. The converter has 16
42 - MC13783:
47 0 Battery Voltage (BATT) 2.50 - 4.65V -2.40V
48 1 Battery Current (BATT - BATTISNS) -50 - 50 mV x20
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| D | f71805f.rst | 44 -----------
57 The Fintek F71806F/FG Super-I/O chip is essentially the same as the
60 The driver assumes that no more than one chip is present, which seems
65 ------------------
67 Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported
68 range is thus from 0 to 2.040 V. Voltage values outside of this range
70 the chip's own power source (+3.3V), and is divided internally by a
83 in0 VCC VCC3.3V int. int. 2.00 1.65 V
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
85 in2 VIN2 VRAM 100K 100K 2.00 ~1.25 V [1]_
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| D | w83781d.rst | 10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
12 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83781d.pdf
18 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
28 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83783s.pdf
34 Addresses scanned: I2C 0x28 - 0x2f
42 - Frodo Looijaard <frodol@dds.nl>,
43 - Philip Edelbrock <phil@netroedge.com>,
44 - Mark Studebaker <mdsxyz123@yahoo.com>
47 -----------------
50 (default 1)
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| D | gl518sm.rst | 21 - Frodo Looijaard <frodol@dds.nl>,
22 - Kyösti Mälkki <kmalkki@cc.hut.fi>
23 - Hong-Gunn Chew <hglinux@gunnet.org>
24 - Jean Delvare <jdelvare@suse.de>
27 -----------
31 For the revision 0x00 chip, the in0, in1, and in2 values (+5V, +3V,
32 and +12V) CANNOT be read. This is a limitation of the chip, not the driver.
46 situation. Measurements are guaranteed between -10 degrees and +110
47 degrees, with a accuracy of +/-3 degrees.
51 case when you have selected to turn fan1 off, no fan1 alarm is triggered.
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| D | sysfs-interface.rst | 5 through the sysfs interface. Since lm-sensors 3.0.0, libsensors is
6 completely chip-independent. It assumes that all the kernel drivers
10 This is a major improvement compared to lm-sensors 2.
13 There is no standard that ensures, for example, that the second
17 voltages between 0 and +4V. Other voltages are scaled back into that
22 For this reason, even if we aim at a chip-independent libsensors, it will
37 Up to lm-sensors 3.0.0, libsensors looks for hardware monitoring attributes
38 in the "physical" device directory. Since lm-sensors 3.0.1, attributes found
50 threshold, "min" (low threshold). Numbering usually starts from 1,
55 they have a simple name, and no number.
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| D | lm78.rst | 6 * National Semiconductor LM78 / LM78-J
10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
20 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
28 - Frodo Looijaard <frodol@dds.nl>
29 - Jean Delvare <jdelvare@suse.de>
32 -----------
34 This driver implements support for the National Semiconductor LM78, LM78-J
37 There is almost no difference between the three supported chips. Functionally,
38 the LM78 and LM78-J are exactly identical. The LM79 has one more VID line,
51 between -55 and +125 degrees, with a resolution of 1 degree.
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| /Documentation/userspace-api/media/cec/ |
| D | cec-ioc-dqevent.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 CEC_DQEVENT - Dequeue a CEC event
35 non-blocking mode and no event is pending, then it will return -1 and
38 The internal event queues are per-filehandle and per-event type. If
39 there is no more room in a queue then the last event is overwritten with
43 two :ref:`CEC_EVENT_STATE_CHANGE <CEC-EVENT-STATE-CHANGE>` events with
51 .. flat-table:: struct cec_event_state_change
52 :header-rows: 0
53 :stub-columns: 0
54 :widths: 1 1 8
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| /Documentation/arch/riscv/ |
| D | hwprobe.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
25 have the same value. Otherwise -1 will be returned. For boolean-like keys, the
33 by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
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| /Documentation/devicetree/bindings/mmc/ |
| D | marvell,xenon-sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
29 - items:
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| D | mmc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
26 const: 1
30 "#size-cells":
37 broken-cd:
40 There is no card detection available; polling must be used.
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| D | brcm,iproc-sdhci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,iproc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
12 - Nicolas Saenz Julienne <nsaenz@kernel.org>
15 - $ref: mmc-controller.yaml#
20 - brcm,bcm2835-sdhci
21 - brcm,bcm2711-emmc2
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| /Documentation/devicetree/bindings/sound/ |
| D | st,sta32x.txt | 7 - compatible: "st,sta32x"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - Vdda-supply: regulator spec, providing 3.3V
17 - Vdd3-supply: regulator spec, providing 3.3V
18 - Vcc-supply: regulator spec, providing 5V - 26V
22 - clocks, clock-names: Clock specifier for XTI input clock.
24 and disabled when it is removed. The 'clock-names' must be set to 'xti'.
26 - st,output-conf: number, Selects the output configuration:
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| D | st,sta350.txt | 7 - compatible: "st,sta350"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - vdd-dig-supply: regulator spec, providing 3.3V
17 - vdd-pll-supply: regulator spec, providing 3.3V
18 - vcc-supply: regulator spec, providing 5V - 26V
22 - st,output-conf: number, Selects the output configuration:
23 0: 2-channel (full-bridge) power, 2-channel data-out
24 1: 2 (half-bridge). 1 (full-bridge) on-board power
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,mxs-pinctrl.txt | 6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
13 Please refer to pinctrl-bindings.txt in this directory for details of the
19 In other words, a subnode that describes a drive strength parameter implies no
20 information about pull-up. For this reason, even seemingly boolean values are
23 values 0 and 1.
32 On mxs, there is no hardware pin group. The pin group in this binding only
34 particular function, like SSP0 functioning as mmc0-8bit. That said, the
37 "pinctrl-*" phandle in client device node should only have one group node
[all …]
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| /Documentation/ |
| D | atomic_t.txt | 9 ---
14 Non-RMW ops:
60 -----
63 respectively (for hysterical raisins), the kernel uses -fno-strict-overflow
64 (which implies -fwrapv) and defines signed overflow to behave like
65 2s-complement.
68 unnecessary and we can simply cast, there is no UB.
70 There was a bug in UBSAN prior to GCC-8 that would generate UB warnings for
78 ---------
80 Non-RMW ops:
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| /Documentation/userspace-api/media/v4l/ |
| D | subdev-formats.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-mbus-format:
14 .. flat-table:: struct v4l2_mbus_framefmt
15 :header-rows: 0
16 :stub-columns: 0
17 :widths: 1 1 2
19 * - __u32
20 - ``width``
21 - Image width in pixels.
22 * - __u32
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| D | metafmt-vsp1-hgo.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
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| /Documentation/devicetree/bindings/leds/backlight/ |
| D | mps,mp3309c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Flavio Suligoi <f.suligoi@asem.it>
13 The Monolithic Power (MPS) MP3309C is a WLED step-up converter, featuring a
17 - analog mode, via I2C commands, as default mode (32 dimming levels)
18 - PWM controlled mode (optional)
24 - $ref: common.yaml#
31 maxItems: 1
35 maxItems: 1
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| /Documentation/devicetree/bindings/riscv/ |
| D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
21 Once a standard extension has been ratified, no changes in behaviour can be
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| /Documentation/userspace-api/media/dvb/ |
| D | dvbstb.svg | 1 <?xml version="1.0" encoding="UTF-8"?>
2 <!-- SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later -->
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| D | ca_high_level.rst | 1 .. SPDX-License-Identifier: GPL-2.0
21 array to/from the CI ioctls as defined in the Linux DVB API. No changes
33 .. code-block:: c
39 #define CA_CI 1 /* CI high level interface */
42 #define CA_DESCR 8 /* built-in descrambler */
46 #define CA_CI_MODULE_PRESENT 1 /* module (or card) inserted */
57 Application layer only and no session management is taken care of by the
61 means that no session management, link layer or a transport layer do
81 .. code-block:: none
84 ----------------------------
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| /Documentation/devicetree/bindings/input/ |
| D | elan,ekth6915.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
14 This touchscreen controller uses the i2c-hid protocol with a reset GPIO.
17 - $ref: /schemas/input/touchscreen/touchscreen.yaml#
22 - items:
23 - enum:
24 - elan,ekth5015m
25 - const: elan,ekth6915
[all …]
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| /Documentation/virt/kvm/devices/ |
| D | arm-vgic-its.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 The ITS allows MSI(-X) interrupts to be injected into guests. This extension is
12 arm-vgic-v3.txt), but does not depend on having physical ITS controllers.
15 a separate, non-overlapping MMIO region.
22 -------------------------
25 KVM_VGIC_ITS_ADDR_TYPE (rw, 64-bit)
33 -E2BIG Address outside of addressable IPA range
34 -EINVAL Incorrectly aligned address
35 -EEXIST Address already configured
36 -EFAULT Invalid user pointer for attr->addr.
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| /Documentation/virt/hyperv/ |
| D | vmbus.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 VMBus is a software construct provided by Hyper-V to guest VMs. It
7 devices that Hyper-V presents to guest VMs. The control path is
11 and the synthetic device implementation that is part of Hyper-V, and
12 signaling primitives to allow Hyper-V and the guest to interrupt
17 establishes the VMBus control path with the Hyper-V host, then
21 Most synthetic devices offered by Hyper-V have a corresponding Linux
29 * PCI device pass-thru
34 * Key/Value Pair (KVP) exchange with Hyper-V
35 * Hyper-V online backup (a.k.a. VSS)
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-zynqmp-fpga | 1 What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
12 BIT(0) 0: No CRC error
13 1: CRC error
15 BIT(1) 0: Decryptor security not set
16 1: Decryptor security set
19 1: MMCMs/PLLs are locked
22 1: DCI matched
24 BIT(4) 0: Start-up sequence has not finished
25 1: Start-up sequence has finished
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