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/Documentation/devicetree/bindings/interrupt-controller/
Dmscc,ocelot-icpu-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi Ocelot SoC ICPU Interrupt Controller
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - $ref: /schemas/interrupt-controller.yaml#
16 the Microsemi Ocelot interrupt controller that is part of the
17 ICPU. It is connected directly to the MIPS core interrupt
23 - enum:
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