Searched full:ordered (Results 1 – 25 of 117) sorted by relevance
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| /Documentation/devicetree/bindings/scsi/ |
| D | hisilicon-sas.txt | 22 sources; the interrupts are ordered in 3 groups, as follows:
30 The phy interrupts are ordered into groups of 3 per phy
34 The interrupts are ordered in increasing order.
35 Fatal interrupts : the fatal interrupts are ordered as follows:
39 the interrupts are ordered in 3 groups, as follows:
47 interrupt. The interrupts are ordered in increasing
50 interrupt source. The interrupts are ordered in
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| /Documentation/arch/riscv/ |
| D | uabi.rst | 26 ordered first by category, in canonical order, as listed above, then
31 extensions are listed, they will be ordered alphabetically.
35 extensions are listed, they will be ordered alphabetically.
39 ordered alphabetically.
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| /Documentation/devicetree/bindings/sound/ |
| D | sirf-audio-port.txt | 6 - dmas: List of DMA controller phandle and DMA request line ordered pairs.
8 These strings correspond 1:1 with the ordered pairs in dmas.
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| D | brcm,bcm2835-i2s.txt | 7 - dmas: List of DMA controller phandle and DMA request line ordered pairs.
9 These strings correspond 1:1 with the ordered pairs in dmas.
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| D | sprd-pcm.txt | 5 - dmas: Specify the list of DMA controller phandle and DMA request line ordered pairs.
7 These strings correspond 1:1 with the ordered pairs in dmas.
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| /Documentation/ |
| D | atomic_t.txt | 156 atomic variable) can be fully ordered and no intermediate state is lost or
169 - RMW operations that have a return value are fully ordered;
183 Fully ordered primitives are ordered against everything prior and everything
184 subsequent. Therefore a fully ordered primitive is like having an smp_mb()
198 ordered, so it is advisable to place the barrier right next to the RMW atomic
203 provide full ordered atomics and these barriers are no-ops.
205 NOTE: when the atomic RmW ops are fully ordered, they should also imply a
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| D | atomic_bitops.txt | 59 - RMW operations that have a return value are fully ordered.
61 - RMW operations that are conditional are fully ordered.
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| /Documentation/litmus-tests/ |
| D | README | 18 the RMW are ordered before the subsequential memory accesses.
24 cmpxchg-fail-ordered-1.litmus
28 cmpxchg-fail-ordered-2.litmus
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| /Documentation/devicetree/bindings/ |
| D | dts-coding-style.rst | 51 ordered by unit address in ascending order.
56 2. Nodes without unit addresses shall be ordered alpha-numerically by the node
57 name. For a few node types, they can be ordered by the main property, e.g.
58 pin configuration states ordered by value of "pins" property.
61 ordered either alpha-numerically or by keeping the order from DTSI, where
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| D | resource-names.txt | 1 Some properties contain an ordered list of 1 or more datum which are
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| /Documentation/core-api/ |
| D | refcount-vs-atomic.rst | 67 then further stores are ordered against this operation.
135 * fully ordered --> control dependency on success for stores
151 * fully ordered --> ACQUIRE ordering on success
164 * fully ordered --> RELEASE ordering + ACQUIRE ordering on success
177 * fully ordered --> RELEASE ordering + control dependency
192 * fully ordered --> RELEASE ordering + control dependency + hold
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-input-cros-ec-keyb | 5 ordered by the physical positions of the keys, from left
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| /Documentation/litmus-tests/atomic/ |
| D | cmpxchg-fail-ordered-2.litmus | 1 C cmpxchg-fail-ordered-2
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| D | Atomic-RMW+mb__after_atomic-is-stronger-than-acquire.litmus | 8 * the RMW are ordered before the subsequential memory accesses.
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| D | cmpxchg-fail-ordered-1.litmus | 1 C cmpxchg-fail-ordered-1
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| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | hsta.txt | 16 - interrupts : ordered interrupt mapping for each MSI in the register
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| /Documentation/admin-guide/perf/ |
| D | nvidia-pmu.rst | 32 strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see
62 In this config, the PMU captures read and relaxed ordered (RO) writes from
123 to local memory. For PCIE traffic, this PMU captures read and relaxed ordered
247 PCIE1 traffic represents strongly ordered (SO) writes.
248 PCIE2 traffic represents reads and relaxed ordered (RO) writes.
298 PCIE1 traffic represents strongly ordered (SO) writes.
299 PCIE2 traffic represents reads and relaxed ordered (RO) writes.
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| /Documentation/devicetree/bindings/clock/ |
| D | lpc1850-cgu.txt | 35 Shall be an ordered list of numbers defining the base clock
38 Shall be an ordered list of strings defining the names of
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| /Documentation/mm/ |
| D | numa.rst | 74 an ordered "zonelist". A zonelist specifies the zones/nodes to visit when a
84 a default Node ordered zonelist. This means it tries to fallback to other zones
85 from the same node before using remote nodes which are ordered by NUMA distance.
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| /Documentation/devicetree/bindings/hwmon/ |
| D | gpio-fan.yaml | 19 ordered MSB-->LSB.
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| /Documentation/networking/ |
| D | sctp.rst | 12 transparent multi-homing, and multiple ordered streams of messages.
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| /Documentation/admin-guide/ |
| D | ext4.rst | 92 * efficient new ordered mode in JBD2 and ext4 (avoid using buffer head to force
177 data=ordered (*)
242 ordered mode.
244 Abort the journal if an error occurs in a file data buffer in ordered
325 the next journal commit, in the default data=ordered mode, the data
407 * ordered mode
409 In data=ordered mode, ext4 only officially journals metadata, but it logically
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| /Documentation/devicetree/bindings/display/panel/ |
| D | sharp,ls037v7dw01.yaml | 35 GPIO ordered MO, LR, and UD as specified in LS037V7DW01.pdf
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| /Documentation/translations/zh_CN/mm/ |
| D | numa.rst | 63 代表了相对稀缺的资源。Linux选择了一个默认的Node ordered zonelist。这意味着在使用按NUMA距
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| /Documentation/devicetree/bindings/usb/ |
| D | ux500-usb.txt | 13 - dma-names : An ordered list of channel names affiliated to the above
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