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/Documentation/devicetree/bindings/extcon/
Dextcon-max3355.txt1 Maxim Integrated MAX3355 USB OTG chip
2 -------------------------------------
5 integrated USB OTG dual-role transceiver to function as a USB OTG dual-role
9 - compatible: should be "maxim,max3355";
10 - maxim,shdn-gpios: should contain a phandle and GPIO specifier for the GPIO pin
12 - id-gpios: should contain a phandle and GPIO specifier for the GPIO pin
17 usb-otg {
19 maxim,shdn-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
20 id-gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>;
Dextcon-palmas.txt5 - compatible: should contain one of:
6 * "ti,palmas-usb-vid".
7 * "ti,twl6035-usb-vid".
8 * "ti,palmas-usb" (DEPRECATED - use "ti,palmas-usb-vid").
9 * "ti,twl6035-usb" (DEPRECATED - use "ti,twl6035-usb-vid").
12 - ti,wakeup : To enable the wakeup comparator in probe
13 - ti,enable-id-detection: Perform ID detection. If id-gpio is specified
14 it performs id-detection using GPIO else using OTG core.
15 - ti,enable-vbus-detection: Perform VBUS detection.
16 - id-gpio: gpio for GPIO ID detection. See gpio binding.
[all …]
/Documentation/devicetree/bindings/phy/
Dallwinner,suniv-f1c100s-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,suniv-f1c100s-usb-phy
24 reg-names:
29 description: USB OTG PHY bus clock
[all …]
Dallwinner,sun8i-v3s-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-v3s-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-v3s-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU0 registers
[all …]
Dallwinner,sun5i-a13-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun5i-a13-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun5i-a13-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU1 registers
[all …]
Dallwinner,sun8i-a23-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a23-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-a23-usb-phy
20 - allwinner,sun8i-a33-usb-phy
24 - description: PHY Control registers
[all …]
Dallwinner,sun50i-a64-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun20i-d1-usb-phy
20 - allwinner,sun50i-a64-usb-phy
24 - description: PHY Control registers
[all …]
Dallwinner,sun50i-h6-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun50i-h6-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU0 registers
[all …]
Dallwinner,sun6i-a31-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun6i-a31-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU1 registers
[all …]
Dallwinner,sun8i-r40-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-r40-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-r40-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU0 registers
[all …]
Dallwinner,sun8i-a83t-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-a83t-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU1 registers
[all …]
Dallwinner,sun4i-a10-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun4i-a10-usb-phy
20 - allwinner,sun7i-a20-usb-phy
24 - description: PHY Control registers
[all …]
Dallwinner,sun8i-h3-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-h3-usb-phy
20 - allwinner,sun50i-h616-usb-phy
24 - description: PHY Control registers
[all …]
Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/Documentation/devicetree/bindings/power/supply/
Drichtek,rt9467.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
11 - ChiaEn Wu <chiaen_wu@richtek.com>
14 RT9467 is a switch-mode single cell Li-Ion/Li-Polymer battery charger for
16 MOSFETs, input current sensing and regulation, high-accuracy voltage
20 The RT9467 also features USB On-The-Go (OTG) support. It also integrates
21 D+/D- pin for USB host/charging port detection.
24 https://www.richtek.com/assets/product_file/RT9467/DS9467-01.pdf
[all …]
Drichtek,rt9471.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alina Yu <alina_yu@richtek.com>
11 - ChiYuan Huang <cy_huang@richtek.com>
14 RT9471 is a switch-mode single cell Li-Ion/Li-Polymer battery charger for
19 https://www.richtek.com/assets/product_file/RT9471=RT9471D/DS9471D-02.pdf
28 charge-enable-gpios:
29 description: GPIO used to turn on and off charging.
32 wakeup-source: true
[all …]
Dbq24190.yaml1 # SPDX-License-Identifier: GPL-2.0
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI BQ2419x Li-Ion Battery Charger
11 - Sebastian Reichel <sre@kernel.org>
14 - $ref: power-supply.yaml#
19 - ti,bq24190
20 - ti,bq24192
21 - ti,bq24192i
22 - ti,bq24196
[all …]
/Documentation/firmware-guide/acpi/
Dextcon-intel-int3496.rst6 devices with an acpi-id of INT3496, such as found for example on
9 This ACPI device describes how the OS can read the id-pin of the devices'
10 USB-otg port, as well as how it optionally can enable Vbus output on the
11 otg port and how it can optionally control the muxing of the data pins
15 to 3 gpio descriptors from its ACPI _CRS (Current Resource Settings) call:
18 Index 0 The input gpio for the id-pin, this is always present and valid
19 Index 1 The output gpio for enabling Vbus output from the device to the otg
20 port, write 1 to enable the Vbus output (this gpio descriptor may
22 Index 2 The output gpio for muxing of the data pins between the USB host and
27 There is a mapping between indices and GPIO connection IDs as follows
/Documentation/devicetree/bindings/usb/
Dmediatek,musb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek MUSB DRD/OTG Controller
11 - Min Guo <min.guo@mediatek.com>
15 pattern: '^usb@[0-9a-f]+$'
19 - enum:
20 - mediatek,mt8516-musb
21 - mediatek,mt2701-musb
22 - mediatek,mt7623-musb
[all …]
Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
27 - mediatek,mt8186-mtu3
[all …]
Dusb-nop-xceiv.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/usb-nop-xceiv.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 const: usb-nop-xceiv
19 clock-names:
22 clock-frequency: true
24 '#phy-cells':
27 vcc-supply:
[all …]
/Documentation/devicetree/bindings/mfd/
Drockchip,rk816.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Zhong <zyw@rock-chips.com>
11 - Zhang Qing <zhangqing@rock-chips.com>
15 that includes regulators, a RTC, a GPIO controller, a power button, and a
21 - rockchip,rk816
29 '#clock-cells':
31 See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
34 clock-output-names:
[all …]

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