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/Documentation/devicetree/bindings/nvmem/
Drockchip,otp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip internal OTP (One Time Programmable) memory
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-otp
16 - rockchip,rk3308-otp
17 - rockchip,rk3588-otp
20 maxItems: 1
[all …]
Dlpc1850-otp.txt1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
7 - reg: Must contain an entry with the physical base address and length
8 for each entry in reg-names.
9 - address-cells: must be set to 1.
10 - size-cells: must be set to 1.
15 otp: otp@40045000 {
16 compatible = "nxp,lpc1850-otp";
18 #address-cells = <1>;
[all …]
Dnintendo-otp.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nintendo Wii and Wii U OTP
10 This binding represents the OTP memory as found on a Nintendo Wii or Wii U,
11 which contains common and per-console keys, signatures and related data
14 See https://wiiubrew.org/wiki/Hardware/OTP
17 - Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
20 - $ref: nvmem.yaml#
[all …]
Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
19 - $ref: nvmem.yaml#
20 - $ref: nvmem-deprecated-cells.yaml#
[all …]
Dmicrochip,lan9662-otpc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/microchip,lan9662-otpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN9662 OTP Controller (OTPC)
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 OTP controller drives a NVMEM memory where system specific data
18 - $ref: nvmem.yaml#
23 - items:
24 - const: microchip,lan9668-otpc
[all …]
Dvf610-ocotp.txt1 On-Chip OTP Memory for Freescale Vybrid
5 - "fsl,vf610-ocotp", "syscon" for VF5xx/VF6xx
6 #address-cells : Should be 1
7 #size-cells : Should be 1
8 reg : Address and length of OTP controller and fuse map registers
14 compatible = "fsl,vf610-ocotp", "syscon";
15 #address-cells = <1>;
16 #size-cells = <1>;
Dsunplus,sp7021-ocotp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/nvmem/sunplus,sp7021-ocotp.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: On-Chip OTP Memory for Sunplus SP7021
11 - Vincent Shih <vincent.sunplus@gmail.com>
14 - $ref: nvmem.yaml#
15 - $ref: nvmem-deprecated-cells.yaml#
19 const: sunplus,sp7021-ocotp
24 reg-names:
[all …]
Dmicrochip,sama7g5-otpc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/microchip,sama7g5-otpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip SAMA7G5 OTP Controller (OTPC)
10 - Claudiu Beznea <claudiu.beznea@microchip.com>
13 OTP controller drives a NVMEM memory where system specific data
18 - $ref: nvmem.yaml#
19 - $ref: nvmem-deprecated-cells.yaml#
24 - const: microchip,sama7g5-otpc
[all …]
Dimx-ocotp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX On-Chip OTP Controller (OCOTP)
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 This binding represents the on-chip eFuse OTP controller found on
20 - $ref: nvmem.yaml#
[all …]
Dmxs-ocotp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/mxs-ocotp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: On-Chip OTP Memory for Freescale i.MX23/i.MX28
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 - $ref: nvmem.yaml#
16 - $ref: nvmem-deprecated-cells.yaml#
[all …]
/Documentation/devicetree/bindings/mtd/
Dmtd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
21 User-defined MTD device name. Can be used to assign user friendly
26 '#address-cells':
29 '#size-cells':
36 - compatible
39 "@[0-9a-f]+$":
[all …]
/Documentation/devicetree/bindings/regulator/
Dpalmas-pmic.txt3 The tps659038 for the AM57x class have OTP spins that
5 is not a need to add the OTP spins to the palmas driver. The
11 - compatible : Should be from the list
12 ti,twl6035-pmic
13 ti,twl6036-pmic
14 ti,twl6037-pmic
15 ti,tps65913-pmic
16 ti,tps65914-pmic
17 ti,tps65917-pmic
18 ti,tps659038-pmic
[all …]
/Documentation/devicetree/bindings/nvmem/layouts/
Dkontron,sl28-vpd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/kontron,sl28-vpd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVMEM layout of the Kontron SMARC-sAL28 vital product data
10 - Michael Walle <michael@walle.cc>
15 on-board ethernet devices are derived from this base MAC address by
22 const: kontron,sl28-vpd
24 serial-number:
30 base-mac-address:
[all …]
Donie,tlv-layout.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/onie,tlv-layout.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
14 infrastructure shall provide a non-volatile memory with a table whose the
26 const: onie,tlv-layout
28 product-name:
32 part-number:
36 serial-number:
[all …]
/Documentation/devicetree/bindings/net/
Dmicrochip,lan78xx.txt3 The LAN78XX devices are usually configured by programming their OTP or with
5 The Device Tree properties, if present, override the OTP and EEPROM.
8 - compatible: Should be one of "usb424,7800", "usb424,7801" or "usb424,7850".
14 - microchip,led-modes: a 0..4 element vector, with each element configuring
16 are defined in "include/dt-bindings/net/microchip-lan78xx.h".
22 usb-port@1 {
24 reg = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
28 usb-port@1 {
[all …]
/Documentation/devicetree/bindings/watchdog/
Ddlg,da9062-watchdog.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/dlg,da9062-watchdog.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Dialog Semiconductor DA906{1,2,3} Watchdog Timer
10 - Steve Twiss <stwiss.opensource@diasemi.com>
13 - $ref: watchdog.yaml#
18 - enum:
19 - dlg,da9062-watchdog
20 - dlg,da9063-watchdog
[all …]
/Documentation/devicetree/bindings/mfd/
Drohm,bd71847-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71847-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
14 single-core, dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is
18 …/www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applica…
19 …//www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applic…
24 - rohm,bd71847
25 - rohm,bd71850
[all …]
Drohm,bd71837-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71837-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
13 BD71837MWV is programmable Power Management ICs for powering single-core,
14 dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is optimized for low
18 …/www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applica…
27 maxItems: 1
30 maxItems: 1
[all …]
Dpalmas.txt3 The TI palmas family current members :-
12 - compatible : Should be from the list
23 - interrupt-controller : palmas has its own internal IRQs
24 - #interrupt-cells : should be set to 2 for IRQ number and flags
27 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
30 ti,mux-padX : set the pad register X (1-2) to the correct muxing for the
31 hardware, if not set will use muxing in OTP.
38 interrupt-parent = <&intc>;
39 interrupt-controller;
40 #interrupt-cells = <2>;
[all …]
/Documentation/hwmon/
Dsht15.rst35 http://www.sensirion.ch/en/pdf/product_information/Datasheet-humidity-sensor-SHT1x.pdf
38 -----------
48 The humidity calibration coefficients are programmed into an OTP memory on the
62 -------------
67 flag to indicate not to reload from OTP (default to false).
72 ---------------
77 heater_enable write 1 in this attribute to enable the on-chip heater,
80 temp1_fault if 1, this means that the voltage is low (below 2.47V) and
/Documentation/ABI/testing/
Dsysfs-platform-silicom1 What: /sys/devices/platform/silicom-platform/uc_version
4 Contact: Henry Shi <henrys@silicom-usa.com>
9 What: /sys/devices/platform/silicom-platform/power_cycle
12 Contact: Henry Shi <henrys@silicom-usa.com>
15 Default value is 0; when set to 1, it powers down
19 0 - default value.
21 What: /sys/devices/platform/silicom-platform/efuse_status
24 Contact: Henry Shi <henrys@silicom-usa.com>
27 OTP status:
29 0 - not programmed.
[all …]
/Documentation/devicetree/bindings/hwinfo/
Dsamsung,exynos-chipid.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/hwinfo/samsung,exynos-chipid.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - enum:
16 - samsung,exynos4210-chipid
17 - samsung,exynos850-chipid
18 - items:
19 - enum:
[all …]
/Documentation/w1/slaves/
Dw1_ds2406.rst12 -----------
15 These chips also provide 128 bytes of OTP EPROM, but reading/writing it is
16 not supported. In TSOC-6 form, the DS2406 provides two switch outputs and
17 can be provided with power on a dedicated input. In TO-92 form, it provides
21 current state of each switch, with PIO A in bit 0 and PIO B in bit 1. The
22 driver ORs this state with 0x30, so shell scripts get an ASCII 0/1/2/3 to
23 work with. output is writable; bits 0 and 1 control PIO A and B,
24 respectively. Bits 2-7 are ignored, so it's safe to write ASCII data.
/Documentation/devicetree/bindings/input/
Dti,palmas-pwrbutton.txt10 - compatible: should be one of the following
11 - "ti,palmas-pwrbutton": For Palmas compatible power on button
12 - interrupts: Interrupt number of power button submodule on device.
16 - ti,palmas-long-press-seconds: Duration in seconds which the power
18 NOTE: This depends on OTP support and POWERHOLD signal configuration
20 - ti,palmas-pwron-debounce-milli-seconds: Duration in milliseconds
29 compatible = "ti,palmas-pwrbutton";
30 interrupt-parent = <&tps659038>;
31 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
32 ti,palmas-long-press-seconds = <12>;
[all …]
/Documentation/devicetree/bindings/net/wireless/
Dmediatek,mt76.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Felix Fietkau <nbd@nbd.name>
12 - Lorenzo Bianconi <lorenzo@kernel.org>
13 - Ryder Lee <ryder.lee@mediatek.com>
25 - mediatek,mt76
26 - mediatek,mt7628-wmac
27 - mediatek,mt7622-wmac
[all …]

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