Searched full:otp (Results 1 – 25 of 40) sorted by relevance
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| /Documentation/devicetree/bindings/nvmem/ |
| D | rockchip,otp.yaml | 4 $id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
7 title: Rockchip internal OTP (One Time Programmable) memory
15 - rockchip,px30-otp
16 - rockchip,rk3308-otp
17 - rockchip,rk3588-otp
29 - const: otp
59 - rockchip,px30-otp
60 - rockchip,rk3308-otp
76 - rockchip,rk3588-otp
85 - const: otp
[all …]
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| D | nintendo-otp.yaml | 4 $id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml#
7 title: Nintendo Wii and Wii U OTP
10 This binding represents the OTP memory as found on a Nintendo Wii or Wii U,
14 See https://wiiubrew.org/wiki/Hardware/OTP
25 - nintendo,hollywood-otp
26 - nintendo,latte-otp
39 otp@d8001ec {
40 compatible = "nintendo,latte-otp";
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| D | lpc1850-otp.txt | 1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
15 otp: otp@40045000 {
16 compatible = "nxp,lpc1850-otp";
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| D | brcm,ocotp.txt | 1 Broadcom OTP memory controller
8 - reg: Base address of the OTP controller.
13 otp: otp@301c800 {
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| D | st,stm32-romem.yaml | 11 flash, OTP, read-only HW regs... This contains various information such as:
25 - st,stm32f4-otp
40 st,non-secure-otp:
58 compatible = "st,stm32f4-otp";
69 st,non-secure-otp;
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| D | microchip,lan9662-otpc.yaml | 7 title: Microchip LAN9662 OTP Controller (OTPC)
13 OTP controller drives a NVMEM memory where system specific data
40 otpc: otp@e0021000 {
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| D | vf610-ocotp.txt | 1 On-Chip OTP Memory for Freescale Vybrid
8 reg : Address and length of OTP controller and fuse map registers
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| D | sunplus,sp7021-ocotp.yaml | 8 title: On-Chip OTP Memory for Sunplus SP7021
58 otp: otp@9c00af00 {
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| D | microchip,sama7g5-otpc.yaml | 7 title: Microchip SAMA7G5 OTP Controller (OTPC)
13 OTP controller drives a NVMEM memory where system specific data
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| D | imx-ocotp.yaml | 7 title: Freescale i.MX On-Chip OTP Controller (OCOTP)
15 This binding represents the on-chip eFuse OTP controller found on
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| D | mxs-ocotp.yaml | 7 title: On-Chip OTP Memory for Freescale i.MX23/i.MX28
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| /Documentation/devicetree/bindings/fuse/ |
| D | renesas,rcar-otp.yaml | 4 $id: http://devicetree.org/schemas/fuse/renesas,rcar-otp.yaml#
19 - renesas,r8a779g0-otp # R-CarV4H
20 - renesas,r8a779h0-otp # R-CarV4M
35 otp: otp@e61be000 {
36 compatible = "renesas,r8a779g0-otp";
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| /Documentation/devicetree/bindings/mtd/ |
| D | mtd.yaml | 47 "^otp(-[0-9]+)?$":
57 An OTP memory region. Some flashes provide a one-time-programmable
64 - user-otp
65 - factory-otp
95 otp-1 {
96 compatible = "factory-otp";
105 otp-2 {
106 compatible = "user-otp";
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| D | nand-macronix.txt | 17 - randomizer enable: should be "mxic,enable-randomizer-otp"
25 mxic,enable-randomizer-otp;
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| /Documentation/devicetree/bindings/regulator/ |
| D | palmas-pmic.txt | 3 The tps659038 for the AM57x class have OTP spins that
5 is not a need to add the OTP spins to the palmas driver. The
35 For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
50 ti,smps-range - OTP has the wrong range set for the hardware so override
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| /Documentation/devicetree/bindings/nvmem/layouts/ |
| D | kontron,sl28-vpd.yaml | 49 otp-1 {
50 compatible = "user-otp";
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| D | onie,tlv-layout.yaml | 134 otp {
135 compatible = "user-otp";
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| /Documentation/devicetree/bindings/watchdog/ |
| D | dlg,da9062-watchdog.yaml | 39 default chip's OTP setting for WATCHDOG_SD bit. If this property is NOT
41 chip's OTP settings.
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| /Documentation/devicetree/bindings/net/ |
| D | microchip,lan78xx.txt | 3 The LAN78XX devices are usually configured by programming their OTP or with
5 The Device Tree properties, if present, override the OTP and EEPROM.
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| /Documentation/devicetree/bindings/mfd/ |
| D | rohm,bd71847-pmic.yaml | 46 # power outputs go down and OTP is reload. At the SNVS state all other logic
49 # state. When a reset is done via SNVS state the PMIC OTP data is not reload.
52 # power outputs will be returned to HW control by OTP loading. Thus the reset
69 # bootloader or OTP) is not touched.
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| D | rohm,bd71837-pmic.yaml | 46 # down and OTP is reload. At the SNVS state all other logic and external
49 # reset is done via SNVS state the PMIC OTP data is not reload. This causes
52 # outputs will be returned to HW control by OTP loading. Thus the reset
69 # bootloader or OTP) is not touched.
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| /Documentation/hwmon/ |
| D | sht15.rst | 48 The humidity calibration coefficients are programmed into an OTP memory on the
67 flag to indicate not to reload from OTP (default to false).
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| /Documentation/ABI/testing/ |
| D | sysfs-platform-silicom | 27 OTP status:
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| D | debugfs-turris-mox-rwtm | 9 device's OTP. The message must be exactly 64 bytes
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| /Documentation/devicetree/bindings/hwinfo/ |
| D | samsung,exynos-chipid.yaml | 37 is missing in the CHIPID registers or in the OTP memory.
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