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/Documentation/devicetree/bindings/iio/frequency/
Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
[all …]
Dadi,adf4377.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
11 - Dragos Bogdan <dragos.bogdan@analog.com>
14 The ADF4377 is a high performance, ultralow jitter, dual output integer-N
25 - adi,adf4377
26 - adi,adf4378
31 spi-max-frequency:
37 clock-names:
[all …]
Dadi,adrf6780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,adrf6780
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
38 clock-output-names:
41 adi,vga-buff-en:
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/Documentation/devicetree/bindings/pinctrl/
Dpincfg-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
21 bias-disable:
25 bias-high-impedance:
27 description: high impedance mode ("third-state", "floating")
29 bias-bus-hold:
33 bias-pull-up:
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Dsprd,pinctrl.txt9 driving level": One pin can output 3.0v or 1.8v, depending on the
11 select 3.0v, then the pin can output 3.0v. "system control" is used
16 of them, so we can not make every Spreadtrum-special configuration
35 - input-enable
36 - input-disable
37 - output-high
38 - output-low
39 - bias-pull-up
40 - bias-pull-down
46 and set the pin sleep related configuration as "input-enable", which
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Dmicrochip,pic32-pinctrl.txt3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
12 - compatible: "microchip,pic32mada-pinctrl"
13 - reg: Address range of the pinctrl registers.
14 - clocks: Clock specifier (see clock bindings for details)
16 Required properties for pin configuration sub-nodes:
17 - pins: List of pins to which the configuration applies.
19 Optional properties for pin configuration sub-nodes:
20 ----------------------------------------------------
21 - function: Mux function for the specified pins.
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Dsprd,sc9860-pinctrl.txt7 - compatible: Must be "sprd,sc9860-pinctrl".
8 - reg: The register address of pin controller device.
9 - pins : An array of strings, each string containing the name of a pin.
12 - function: A string containing the name of the function, values must be
14 - drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
16 - input-schmitt-disable: Enable schmitt-trigger mode.
17 - input-schmitt-enable: Disable schmitt-trigger mode.
18 - bias-disable: Disable pin bias.
19 - bias-pull-down: Pull down on pin.
20 - bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
[all …]
Dcanaan,k210-fpioa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
16 a per-pin basis.
20 const: canaan,k210-fpioa
29 - description: Controller reference clock source
30 - description: APB interface clock source
32 clock-names:
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/Documentation/ABI/testing/
Dsysfs-bus-iio-dac3 Contact: linux-iio@vger.kernel.org
5 Toggle enable. Write 1 to enable toggle or 0 to disable it. This
6 is useful when one wants to change the DAC output codes. For
9 - disable toggle operation;
10 - change out_currentY_rawN, where N is the integer value of the symbol;
11 - enable toggle operation.
15 Contact: linux-iio@vger.kernel.org
18 specific to toggle enabled channels and refers to the DAC output
24 Contact: linux-iio@vger.kernel.org
26 Performs a SW switch to a predefined output symbol. This attribute
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Dsysfs-bus-iio-timer-stm328 - "reset"
10 used as trigger output (TRGO).
11 - "enable"
12 The Counter Enable signal CNT_EN is used
13 as trigger output.
14 - "update"
15 The update event is selected as trigger output.
18 - "compare_pulse"
19 The trigger output send a positive pulse
21 - "OC1REF"
[all …]
Dconfigfs-usb-gadget-uac21 What: /config/usb-gadget/gadget/functions/uac2.name
9 c_srate list of capture sampling rates (comma-separated)
11 c_hs_bint capture bInterval for HS/SS (1-4: fixed, 0: auto)
14 c_mute_present capture mute control enable
15 c_volume_present capture volume control enable
24 p_srate list of playback sampling rates (comma-separated)
26 p_hs_bint playback bInterval for HS/SS (1-4: fixed, 0: auto)
27 p_mute_present playback mute control enable
28 p_volume_present playback volume control enable
35 req_number the number of pre-allocated requests
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Dconfigfs-usb-gadget-uac11 What: /config/usb-gadget/gadget/functions/uac1.name
9 c_srate list of capture sampling rates (comma-separated)
11 c_mute_present capture mute control enable
12 c_volume_present capture volume control enable
20 p_srate list of playback sampling rates (comma-separated)
22 p_mute_present playback mute control enable
23 p_volume_present playback volume control enable
30 req_number the number of pre-allocated requests
35 p_ot_name playback output terminal name
39 c_ot_name capture output terminal name
/Documentation/devicetree/bindings/regulator/
Dmediatek,mt6397-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/mediatek,mt6397-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sen Chu <sen.chu@mediatek.com>
11 - Macpaul Lin <macpaul.lin@mediatek.com>
15 All voltage regulators provided by the PMIC are described as sub-nodes of
21 - const: mediatek,mt6397-regulator
29 regulator-allowed-modes:
31 BUCK regulators can set regulator-initial-mode and regulator-allowed-modes to
[all …]
Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
15 (Enable/Fail), Enable pin to turn chip on, and Fail pin as fault indication.
18 supply, vsync input from IR camera, and fsin1/fsin2 output for the optional.
27 wakeup-source: true
32 enable-gpios:
33 description: A connection of the 'enable' gpio line.
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Dawinic,aw37503.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alec Li <like@awinic.com>
14 supply for driving TFT-LCD panels. It support software-configurable output
15 switching and monitoring. The output voltages can be programmed via an I2C
34 enable-gpios:
37 GPIO specifier to enable the GPIO control (on/off) for regulator.
40 - regulator-name
43 - compatible
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Dti,tps62360.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laxman Dewangan <ldewangan@nvidia.com>
13 The TPS6236x are a family of step down dc-dc converter with
15 up to 3A peak load current, and an output voltage range of
22 - $ref: regulator.yaml#
27 - ti,tps62360
28 - ti,tps62361
29 - ti,tps62362
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/Documentation/fb/
Dviafb.rst6 --------
15 ---------------
34 ----------------------
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
53 - 8, 16, 32 (default:32)
56 - 60, 75, 85, 100, 120 (default:60)
59 - 0 : expansion (default)
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/Documentation/devicetree/bindings/display/ti/
Dti,opa362.txt4 - compatible: "ti,opa362"
5 - enable-gpios: enable/disable output gpio
8 - Video port 0 for opa362 input
9 - Video port 1 for opa362 output
15 enable-gpios = <&gpio1 23 0>; /* GPIO to enable video out amplifier */
18 #address-cells = <1>;
19 #size-cells = <0>;
24 remote-endpoint = <&venc_out>;
31 remote-endpoint = <&tv_connector_in>;
/Documentation/devicetree/bindings/clock/
Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
17 - reg : shall be the physical PLL register address for the pll clock.
[all …]
Didt,versaclock5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 clock generators providing from 3 to 12 output clocks.
16 - 5P49V5923:
17 0 -- OUT0_SEL_I2CB
18 1 -- OUT1
19 2 -- OUT2
21 - 5P49V5933:
22 0 -- OUT0_SEL_I2CB
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/Documentation/devicetree/bindings/memory-controllers/
Darm,pl172.txt5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
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/Documentation/devicetree/bindings/net/nfc/
Dnxp,pn544.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: nxp,pn544-i2c
22 enable-gpios:
23 description: Output GPIO pin used for enabling/disabling the PN544
26 firmware-gpios:
27 description: Output GPIO pin used to enter firmware download mode
31 - compatible
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Dnxp,nci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - const: nxp,nxp-nci-i2c
16 - items:
17 - enum:
18 - nxp,nq310
19 - nxp,pn547
20 - const: nxp,nxp-nci-i2c
[all …]
/Documentation/devicetree/bindings/iio/addac/
Dadi,ad74115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74115H is a single-channel software configurable input/output
15 analog output, analog input, digital output, digital input, resistance
17 chip solution with an SPI interface. The device features a 16-bit ADC and a
18 14-bit DAC.
25 - adi,ad74115h
30 spi-max-frequency:
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/Documentation/devicetree/bindings/net/ieee802154/
Dca8210.txt4 - compatible: Should be "cascoda,ca8210"
5 - reg: Controlling chip select
6 - spi-max-frequency: Maximum clock speed, should be *less than*
8 - spi-cpol: Requires inverted clock polarity
9 - reset-gpio: GPIO attached to reset
10 - irq-gpio: GPIO attached to IRQ
12 - extclock-enable: Include for the ca8210 to route its 16MHz clock
13 to an output
14 - extclock-freq: Frequency in Hz of the external clock
15 - extclock-gpio: GPIO of the ca8210 to output the clock on
[all …]

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