Searched full:p15 (Results 1 – 5 of 5) sorted by relevance
| /Documentation/arch/arm64/ |
| D | sve.rst | 25 * SVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, are
114 Z0..Z31 are preserved. All other bits of Z0..Z31, and all of P0..P15 and FFR
258 * Changing the vector length causes all of P0..P15, FFR and all bits of
489 * 16 VL-bit predicate registers P0..P15
529 P15 | | +-------+
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| D | sme.rst | 237 * Changing the vector length causes all of ZA, ZTn, P0..P15, FFR and all
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-pca95xx.yaml | 187 "en-host1", "en-host2", "chg-int", "p14", "p15",
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| /Documentation/trace/coresight/ |
| D | coresight.rst | 436 Instruction 6 0x8026B560 EE1D3F30 false MRC p15,#0x0,r3,c13,c0,#1
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| /Documentation/admin-guide/ |
| D | devices.txt | 1694 15 = /dev/amiraid/ar?p15 15th partition
2259 15 = /dev/emd/0p15 Partition 15 on First unit
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