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/Documentation/devicetree/bindings/interrupt-controller/
Dloongson,pch-pic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCH PIC Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson LS7A family of PCH for
14 transforming interrupts from on-chip devices into HyperTransport vectorized
19 const: loongson,pch-pic-1.0
22 maxItems: 1
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Dloongson,htpic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-3 HyperTransport Interrupt Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 - $ref: /schemas/interrupt-controller.yaml#
16 This interrupt controller is found in the Loongson-3 family of chips to transmit
17 interrupts from PCH PIC connected on HyperTransport bus.
21 const: loongson,htpic-1.0
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/Documentation/translations/zh_TW/arch/loongarch/
Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_TW.rst
5 :Original: Documentation/arch/loongarch/irq-chip-model.rst
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片組的主中
16 斷控制器）、PCH-LPC（LS7A芯片組的LPC中斷控制器）和PCH-MSI（MSI中斷控制器）。
19 全局中斷控制器（每個芯片一個，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在這種模型裏面，IPI（Inter-Processor Interrupt）和CPU本地時鐘中斷直接發送到CPUINTC，
27 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
28 PCH-LPC/PCH-MSI，然後被HTVECINTC統一收集，再發送到LIOINTC，最後到達CPUINTC::
30 +-----+ +---------+ +-------+
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/Documentation/translations/zh_CN/arch/loongarch/
Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
5 :Original: Documentation/arch/loongarch/irq-chip-model.rst
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
30 +-----+ +---------+ +-------+
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/Documentation/arch/loongarch/
Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
27 +-----+ +---------+ +-------+
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