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/Documentation/devicetree/bindings/pci/
Dpci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/pci-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCI Endpoint Controller
10 Common properties for PCI Endpoint Controller Nodes.
13 - Kishon Vijay Abraham I <kishon@kernel.org>
14 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 pattern: "^pcie-ep@"
20 max-functions:
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Dpci.txt1 PCI bus bridges have standardized Device Tree bindings:
3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
15 If present this property assigns a fixed PCI domain number to a host bridge,
18 host bridges in the system, otherwise potentially conflicting domain numbers
19 may be assigned to root buses behind different host bridges. The domain
21 - max-link-speed:
22 If present this property specifies PCI gen for link capability. Host
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Dmediatek-pcie.txt4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
11 - device_type: Must be "pci"
12 - reg: Base addresses and lengths of the root ports.
13 - reg-names: Names of the above areas to use during resource lookup.
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Dbrcm,iproc-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - enum:
22 - brcm,iproc-pcie
23 # for the second generation of PAXB-based controllers, used in
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Dfsl,imx6q-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
22 clock-names:
26 num-lanes:
29 fsl,imx7d-pcie-phy:
31 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
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Dintel-gw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
16 const: intel,lgm-pcie
18 - compatible
21 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 - const: intel,lgm-pcie
27 - const: snps,dw-pcie
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Dcdns,cdns-pcie-host.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: cdns-pcie-host.yaml#
17 const: cdns,cdns-pcie-host
22 reg-names:
24 - const: reg
25 - const: cfg
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Drockchip-dw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
17 snps,dw-pcie.yaml.
20 - $ref: /schemas/pci/snps,dw-pcie.yaml#
21 - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
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Dqcom,pcie-sa8775p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SA8775p PCI Express Root Complex
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 const: qcom,pcie-sa8775p
25 reg-names:
27 - const: parf # Qualcomm specific registers
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Dqcom,pcie-sc8180x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC8180x PCI Express Root Complex
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 const: qcom,pcie-sc8180x
25 reg-names:
28 - const: parf # Qualcomm specific registers
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/Documentation/arch/s390/
Dpci.rst1 .. SPDX-License-Identifier: GPL-2.0
4 S/390 PCI
8 - Pierre Morel
17 -----------------------
21 Do not use PCI Mapped I/O (MIO) instructions.
25 Ignore the RID field and force use of one PCI domain per PCI function.
28 ---------------
36 - /sys/kernel/debug/s390dbf/pci_msg/sprintf
37 Holds messages from the processing of PCI events, like machine check handling
50 * /sys/bus/pci/slots/XXXXXXXX
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/Documentation/translations/zh_CN/PCI/
Dpci-iov-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/PCI/pci-iov-howto.rst
15 .. _cn_pci-iov-howto:
18 PCI Express I/O 虚拟化指南
22 :作者: - Yu Zhao <yu.zhao@intel.com>
23 - Donald Dutile <ddutile@redhat.com>
28 什么是SR-IOV
29 ------------
31 单根I/O虚拟化（SR-IOV）是一种PCI Express扩展功能，它使一个物理设备显示为多个
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/Documentation/ABI/testing/
Dsysfs-driver-pciback1 What: /sys/bus/pci/drivers/pciback/quirks
4 Contact: xen-devel@lists.xenproject.org
7 the format of DDDD:BB:DD.F-REG:SIZE:MASK will allow the guest
8 to write and read from the PCI device. That is Domain:Bus:
9 Device.Function-Register:Size:Mask (Domain is optional).
12 #echo 00:19.0-E0:2:FF > /sys/bus/pci/drivers/pciback/quirks
17 What: /sys/bus/pci/drivers/pciback/allow_interrupt_control
20 Contact: xen-devel@lists.xenproject.org
23 MSI, MSI-X) set by a connected guest. It is meant to be set
Dsysfs-devices-mapping9 For example, on 4-die Xeon platform with up to 6 IIO stacks per
14 -r--r--r-- /sys/devices/uncore_iio_0/die0
15 -r--r--r-- /sys/devices/uncore_iio_0/die1
16 -r--r--r-- /sys/devices/uncore_iio_0/die2
17 -r--r--r-- /sys/devices/uncore_iio_0/die3
31 IIO PMU 0 on die 0 belongs to PCI RP on bus 0x00, domain 0x0000
32 IIO PMU 0 on die 1 belongs to PCI RP on bus 0x40, domain 0x0000
33 IIO PMU 0 on die 2 belongs to PCI RP on bus 0x80, domain 0x0000
34 IIO PMU 0 on die 3 belongs to PCI RP on bus 0xc0, domain 0x0000
44 For example, 4-die Sapphire Rapids platform has the following
Dsysfs-firmware-sgi_uv8 Under that directory are a number of read-only attributes::
18 is used to select arch-dependent addresses and features.
37 domains. The coherence id indicates which coherence domain
59 Each hub object directory contains a number of read-only attributes::
69 If a cnode value is not applicable, the value returned will be -1.
86 If a nasid value is not applicable, the value returned will be -1.
99 Each port object directory contains a number of read-only attributes::
107 the value returned will be -1.
112 returned will be -1.
124 The pcibuses directory contains a number of PCI bus objects.
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Dsysfs-bus-pci1 What: /sys/bus/pci/drivers/.../bind
4 Contact: linux-pci@vger.kernel.org
10 That is Domain:Bus:Device.Function and is the same as
11 found in /sys/bus/pci/devices/. For example::
13 # echo 0000:00:19.0 > /sys/bus/pci/drivers/foo/bind
15 (Note: kernels before 2.6.28 may require echo -n).
17 What: /sys/bus/pci/drivers/.../unbind
20 Contact: linux-pci@vger.kernel.org
26 That is Domain:Bus:Device.Function and is the same as
27 found in /sys/bus/pci/devices/. For example::
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/Documentation/PCI/
Dpci-iov-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
5 PCI Express I/O Virtualization Howto
9 :Authors: - Yu Zhao <yu.zhao@intel.com>
10 - Donald Dutile <ddutile@redhat.com>
15 What is SR-IOV
16 --------------
18 Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended
25 turned on, each VF's PCI configuration space can be accessed by its own
26 Bus, Device and Function Number (Routing ID). And each VF also has PCI
29 real existing PCI device.
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Dsysfs-pci.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Accessing PCI device resources through sysfs
7 sysfs, usually mounted at /sys, provides access to PCI resources on platforms
11 |-- 0000:17:00.0
12 | |-- class
13 | |-- config
14 | |-- device
15 | |-- enable
16 | |-- irq
17 | |-- local_cpus
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/Documentation/devicetree/bindings/virtio/
Dpci-iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/virtio/pci-iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: virtio-iommu device using the virtio-pci transport
10 - Jean-Philippe Brucker <jean-philippe@linaro.org>
13 When virtio-iommu uses the PCI transport, its programming interface is
14 discovered dynamically by the PCI probing infrastructure. However the
16 masters. Therefore, the PCI root complex that hosts the virtio-iommu
20 virtio-iommu node doesn't have an "iommus" property, and is omitted from
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/Documentation/driver-api/pci/
Dp2pdma.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PCI Peer-to-Peer DMA Support
7 The PCI bus has pretty decent support for performing DMA transfers
9 called Peer-to-Peer (or P2P). However, there are a number of issues that
12 One of the biggest issues is that PCI doesn't require forwarding
14 defines a separate hierarchy domain. To make things worse, there is no
18 same PCI bridge, as such devices are all in the same PCI hierarchy
19 domain, and the spec guarantees that all transactions within the
25 pages. However, PCI BARs are not typically cache coherent so there are
36 * Provider - A driver which provides or publishes P2P resources like
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/Documentation/scsi/
Daic7xxx.rst1 .. SPDX-License-Identifier: GPL-2.0
5 Adaptec Aic7xxx Fast -> Ultra160 Family Manager Set v7.0
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
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Daic79xx.rst1 .. SPDX-License-Identifier: GPL-2.0
28 AIC-7901A Single Channel 64-bit PCI-X 133MHz to
30 AIC-7901B Single Channel 64-bit PCI-X 133MHz to
32 AIC-7902A4 Dual Channel 64-bit PCI-X 133MHz to
34 AIC-7902B Dual Channel 64-bit PCI-X 133MHz to
41 Adaptec SCSI Card 39320 Dual Channel 64-bit PCI-X 133MHz to 7902A4/7902B
43 68-pin, two internal 68-pin)
44 Adaptec SCSI Card 39320A Dual Channel 64-bit PCI-X 133MHz to 7902B
46 68-pin, two internal 68-pin)
47 Adaptec SCSI Card 39320D Dual Channel 64-bit PCI-X 133MHz to 7902A4
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/Documentation/virt/hyperv/
Dvpci.rst1 .. SPDX-License-Identifier: GPL-2.0
3 PCI pass-thru devices
5 In a Hyper-V guest VM, PCI pass-thru devices (also called
6 virtual PCI devices, or vPCI devices) are physical PCI devices
16 Hyper-V terminology for vPCI devices is "Discrete Device
17 Assignment" (DDA). Public documentation for Hyper-V DDA is
20 …tps://learn.microsoft.com/en-us/windows-server/virtualization/hyper-v/plan/plan-for-deploying-devi…
23 and for GPUs. A similar mechanism for NICs is called SR-IOV
25 driver to interact directly with the hardware. See Hyper-V
26 public documentation here: `SR-IOV`_
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/Documentation/networking/
Dnet_failover.rst1 .. SPDX-License-Identifier: GPL-2.0
19 'pci' device. The user accesses the network interface via 'failover' netdev.
28 virtio-net accelerated datapath: STANDBY mode
31 net_failover enables hypervisor controlled accelerated datapath to virtio-net
35 feature on the virtio-net interface and assign the same MAC address to both
36 virtio-net and VF interfaces.
49 <alias name='ua-backup0'/>
54 <address type='pci' domain='0x0000' bus='0x42' slot='0x02' function='0x5'/>
56 <teaming type='transient' persistent='ua-backup0'/>
59 In this configuration, the first device definition is for the virtio-net
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/Documentation/arch/x86/
Diommu.rst7 - Intel: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-dire…
8 - AMD: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_3_…
13 -----------
21 - DMAR - Intel DMA Remapping table
22 - DRHD - Intel DMA Remapping Hardware Unit Definition
23 - RMRR - Intel Reserved Memory Region Reporting Structure
24 - IVRS - AMD I/O Virtualization Reporting Structure
25 - IVDB - AMD I/O Virtualization Definition Block
26 - IVHD - AMD I/O Virtualization Hardware Definition
41 The architecture defines an ACPI-compatible data structure called an I/O
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