Searched full:pclk (Results 1 – 25 of 175) sorted by relevance
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| /Documentation/devicetree/bindings/timer/ |
| D | faraday,fttmr010.txt | 23 - clock-names : should be "EXTCLK" and "PCLK" for the external tick timer
36 clocks = <&extclk>, <&pclk>;
37 clock-names = "EXTCLK", "PCLK";
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| D | amlogic,meson6-timer.yaml | 30 - const: pclk
53 clock-names = "xtal", "pclk";
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| /Documentation/devicetree/bindings/rtc/ |
| D | faraday,ftrtc010.yaml | 34 - description: PCLK clocks
41 - const: PCLK
57 clock-names = "PCLK", "EXTCLK";
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| D | cdns,rtc.txt | 11 - pclk: APB registers clock
20 clock-names = "pclk", "ref_clk";
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx8mm-disp-blk-ctrl.yaml | 53 - const: dsi-pclk
56 - const: csi-pclk
91 "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
92 "dsi-ref", "csi-aclk", "csi-pclk";
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| D | fsl,imx8mn-disp-blk-ctrl.yaml | 54 - const: dsi-pclk
57 - const: csi-pclk
94 "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
95 "dsi-ref", "csi-aclk", "csi-pclk";
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| /Documentation/devicetree/bindings/media/ |
| D | microchip,csi2dc.yaml | 57 This is named 'pclk'. The second clock must be the cross domain clock,
63 - const: pclk
148 clocks = <&pclk>, <&scck>;
149 clock-names = "pclk", "scck";
178 clocks = <&pclk>, <&scck>;
179 clock-names = "pclk", "scck";
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| D | st,stm32-dcmipp.yaml | 49 pclk-sample: true
54 - pclk-sample
84 pclk-sample = <0>;
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| /Documentation/devicetree/bindings/serial/ |
| D | amlogic,meson-uart.yaml | 72 - description: the source of the baudrate generator, can be either the xtal or the pclk
77 - const: pclk
100 clocks = <&xtal>, <&pclk>, <&xtal>;
101 clock-names = "xtal", "pclk", "baud";
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| /Documentation/devicetree/bindings/spi/ |
| D | renesas,rzv2m-csi.yaml | 29 - description: Internal clock to access the registers (PCLK)
34 - const: pclk
74 clock-names = "csiclk", "pclk";
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| D | xlnx,zynq-qspi.yaml | 38 - const: pclk
56 clock-names = "ref_clk", "pclk";
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| D | spi-zynqmp-qspi.yaml | 30 - const: pclk
60 clock-names = "ref_clk", "pclk";
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | mt9m111.txt | 18 - pclk-sample: For information see ../video-interfaces.txt. The value is set to
33 pclk-sample = <1>;
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| D | tvp514x.txt | 21 - pclk-sample: Clock polarity of the endpoint.
39 pclk-sample = <0>;
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| /Documentation/devicetree/bindings/net/ |
| D | cortina,gemini-ethernet.yaml | 64 description: this should contain a handle to the PCLK clock for
68 const: PCLK
121 clock-names = "PCLK";
134 clock-names = "PCLK";
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| /Documentation/devicetree/bindings/phy/ |
| D | rockchip,pcie3-phy.yaml | 85 - const: pclk
95 - const: pclk
109 clock-names = "refclk_m", "refclk_n", "pclk";
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| D | amlogic,axg-mipi-dphy.yaml | 26 - const: pclk
64 clock-names = "pclk";
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| /Documentation/devicetree/bindings/i2c/ |
| D | socionext,synquacer-i2c.yaml | 26 const: pclk
54 clock-names = "pclk";
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| /Documentation/devicetree/bindings/i3c/ |
| D | cdns,i3c-master.yaml | 27 - const: pclk
47 clock-names = "pclk", "sysclk";
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| D | silvaco,i3c-master.yaml | 33 - const: pclk
54 clock-names = "pclk", "fast_clk", "slow_clk";
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| /Documentation/devicetree/bindings/usb/ |
| D | atmel-usb.txt | 66 "pclk" for the peripheral clock
78 clock-names = "pclk", "hclk";
97 "pclk" for the peripheral clock
123 clock-names = "hclk", "pclk";
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | microchip,sam9x75-lvds.yaml | 34 - const: pclk
54 clock-names = "pclk";
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| /Documentation/devicetree/bindings/watchdog/ |
| D | faraday,ftwdt010.yaml | 40 const: PCLK
65 clock-names = "PCLK";
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| D | st,stm32-iwdg.yaml | 35 - pclk
60 clock-names = "pclk", "lsi";
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| /Documentation/devicetree/bindings/sound/ |
| D | amlogic,t9015.yaml | 32 - const: pclk
67 clock-names = "pclk";
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